公开(公告)号：US20180190604A1

公开(公告)日：2018-07-05

申请号：US15394460

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： Mihir A. OKA ,  Ken P. HACKENBERG ,  Vijay Krishnan (Vijay) SUBRAMANIAN ,  Neha M. PATEL ,  Nachiket R. RARAVIKAR

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/02311 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/211 ,  H01L2924/014 ,  H01L2924/3841

Abstract: Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.

公开(公告)号：US20190157225A1

公开(公告)日：2019-05-23

申请号：US16260908

申请日：2019-01-29

Applicant: Intel Corporation

Inventor： Mihir A. OKA ,  Ken P. HACKENBERG ,  Vijay Krishnan (Vijay) SUBRAMANIAN ,  Neha M. PATEL ,  Nachiket R. RARAVIKAR

IPC: H01L23/00

Abstract: Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.

公开(公告)号：US20210195798A1

公开(公告)日：2021-06-24

申请号：US16723865

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Nicholas NEAL ,  Nicholas S. HAEHN ,  Je-Young CHANG ,  Kyle ARRINGTON ,  Aaron MCCANN ,  Edvin CETEGEN ,  Ravindranath V. MAHAJAN ,  Robert L. SANKMAN ,  Ken P. HACKENBERG ,  Sergio A. CHAN ARGUEDAS

IPC: H05K7/20 ,  H01L23/367 ,  H01L23/00 ,  H01L23/498

Abstract: Embodiments include semiconductor packages. A semiconductor package includes dies on a package substrate, an integrated heat spreader (IHS) with a lid and sidewalls over the dies and package substrate, and a heatsink and a thermal interface material respectively on the IHS. The semiconductor package includes a vapor chamber defined by a surface of the package substrate and surfaces of the lid and sidewalls, and a wick layer in the vapor chamber. The wick layer is on the dies, package substrate, and IHS, where the vapor chamber has a vapor space defined by surfaces of the wick layer and lid of the IHS. The sidewalls are coupled to the package substrate with a sealant that hermetically seals the vapor chamber with the surfaces of the package substrate and the sidewalls and lid. The wick layer has a uniform or non-uniform thickness, and has porous materials including metals, powders, or graphite.

公开(公告)号：US20190267306A1

公开(公告)日：2019-08-29

申请号：US16343703

申请日：2016-12-07

Applicant: Intel Corporation

Inventor： Nachiket R. RARAVIKAR ,  Ravindranath V. MAHAJAN ,  Robert L. SANKMAN ,  James C. MATAYABAS, Jr. ,  Ken P. HACKENBERG ,  Nayandeep K. MAHANTA ,  David D. OLMOZ

IPC: H01L23/373 ,  H01L23/42 ,  H01L23/367

Abstract: In some embodiments a semiconductor die package includes a package substrate, a plurality of dies each attached to the package substrate, a layer of a thermally conducting sintered paste over the top of each die, a layer of flexible polymer thermal interface material over the sintered paste, and a heat spreader over and thermally connected to the polymer thermal interface material.