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    SYSTEMS, METHODS, AND APPARATUSES FOR IMPLEMENTING A THERMAL SOLUTION FOR 3D PACKAGING
    4.
    发明申请
    SYSTEMS, METHODS, AND APPARATUSES FOR IMPLEMENTING A THERMAL SOLUTION FOR 3D PACKAGING 审中-公开

    公开(公告)号：US20190043772A1

    公开(公告)日：2019-02-07

    申请号：US16075120

    申请日：2016-04-02

    Applicant: Intel Corporation

    Inventor： Purushotham Kaushik MUTHUR SRINATH ,  Pramod MALATKAR ,  Sairam AGRAHARAM ,  Chandra M. JHA ,  Arnab CHOUDHURY ,  Nachiket R. RARAVIKAR

    IPC: H01L23/26 ,  H01L23/433

    Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a thermal solution for 3D packaging. For instance, in accordance with one embodiment, there is an apparatus having therein: a substrate layer having electrical traces therein; a first layer functional silicon die electrically interfaced to the electrical traces of the substrate layer, the first layer functional silicon die having a first thermal pad integrated thereupon; a second layer functional silicon die positioned above the first layer functional silicon die, the second layer functional silicon die having a second thermal pad integrated thereupon; and a conductivity layer positioned between the first layer functional silicon die and the second layer functional silicon die, wherein the conductivity layer is to: (i) electrically join the second layer functional silicon die to the first layer functional silicon die and (ii) bond the first thermal pad of the first layer functional silicon die to the second thermal pad of the second layer functional silicon die via solder. Other related embodiments are disclosed.

    SINTERED SOLDER FOR FINE PITCH FIRST-LEVEL INTERCONNECT (FLI) APPLICATIONS
    8.
    发明申请
    SINTERED SOLDER FOR FINE PITCH FIRST-LEVEL INTERCONNECT (FLI) APPLICATIONS 审中-公开

    公开(公告)号：US20190157225A1

    公开(公告)日：2019-05-23

    申请号：US16260908

    申请日：2019-01-29

    Applicant: Intel Corporation

    Inventor： Mihir A. OKA ,  Ken P. HACKENBERG ,  Vijay Krishnan (Vijay) SUBRAMANIAN ,  Neha M. PATEL ,  Nachiket R. RARAVIKAR

    IPC: H01L23/00

    Abstract: Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.

    NOVEL METHOD AND MATERIALS FOR WARPAGE THERMAL AND INTERCONNECT SOLUTIONS
    10.
    发明申请
    NOVEL METHOD AND MATERIALS FOR WARPAGE THERMAL AND INTERCONNECT SOLUTIONS 审中-公开

    公开(公告)号：US20170200621A1

    公开(公告)日：2017-07-13

    申请号：US15469284

    申请日：2017-03-24

    Applicant: Intel Corporation

    Inventor： Omkar G. KARHADE ,  Nitin A. DESHPANDE, JR. ,  Aditya Sundoctor VAIDYA ,  Nachiket R. RARAVIKAR ,  Eric J. LI

    IPC: H01L21/56 ,  H01L21/768 ,  H01L21/78

    Abstract: Embodiments describe a semiconductor package that includes a substrate, a die bonded to the substrate, and a solder paste overmold layer formed over a top surface of the die. In an embodiment, the solder paste comprises a high-melting point metal, a solder matrix, intermetallic compounds and a polymer. The overmold layer has a high elastic modulus, a coefficient of thermal expansion similar to the substrate, and reduces the warpage of the package. In an embodiment, interconnects of a semiconductor package are formed with a no-slump solder paste that includes vents. Vents may be formed through a conductive network formed by the high-melting point metal, solder matrix and intermetallic compounds. In an embodiment, vents provide a path through the interconnect that allows for moisture outgassing. In an embodiment, a mold layer may be mechanically anchored to the interconnects by the vents, thereby providing improved mechanical continuity to the mold layer.

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