-
公开(公告)号：US20150154124A1
公开(公告)日：2015-06-04
申请号：US14093772
申请日：2013-12-02
Applicant: Intel Corporation
Inventor： Shamanna Datta , Mark A. Schmisseur , Murugasamy Nachimuthu , Richard P. Mangold , Mahesh S. Natu
CPC classification number: G06F12/0246 , G06F12/084 , G06F2212/7202
Abstract: Apparatus, systems, and methods to implement a secure data partition in memory systems are described. In one example, a controller comprises logic to receive, in a system management mode mailbox, a memory partition creation request from a system management mode interface, wherein the memory partition creation request comprises at least one characteristic of a memory partition, authenticate the partition creation request and create a memory partition in a memory coupled to the controller in accordance with the at least one characteristic. Other examples are also disclosed and claimed.
Abstract translation: 描述了在存储器系统中实现安全数据分区的装置，系统和方法。 在一个示例中，控制器包括在系统管理模式邮箱中从系统管理模式接口接收存储器分区创建请求的逻辑，其中所述存储器分区创建请求包括存储器分区的至少一个特征，认证分区创建 请求并根据该至少一个特性在耦合到控制器的存储器中创建存储器分区。 还公开并要求保护其他实例。
-
公开(公告)号：US20140237299A1
公开(公告)日：2014-08-21
申请号：US13997301
申请日：2011-12-29
Applicant: INTEL CORPORATION
Inventor： Murugasamy Nachimuthu , Mohan J. Kumar , Theodros Yigzaw , Jose A. Vargas , Rajendra Kuramkote
IPC: G06F11/07
CPC classification number: G06F11/0772 , G06F11/0745 , G06F11/3664 , G06F21/57
Abstract: Various embodiments are described herein. Some embodiments include an Operating System and a platform. The platform includes a processor having an error register. The Operating System can write to the error register only via the platform in a secure manner (for example, using platform firmware). Other embodiments are described and claimed.
Abstract translation: 本文描述了各种实施例。 一些实施例包括操作系统和平台。 该平台包括具有错误寄存器的处理器。 操作系统只能通过平台以安全的方式（例如使用平台固件）写入错误寄存器。 描述和要求保护其他实施例。
-
公开(公告)号：US12223308B2
公开(公告)日：2025-02-11
申请号：US18040147
申请日：2020-08-25
Applicant: Intel Corporation
Inventor： Mohan Kumar , Sarathy Jayakumar , Brett Peng Wang , Ashok Raj , Murugasamy Nachimuthu
IPC: G06F8/65 , G06F8/654 , G06F8/656 , G06F9/4401
Abstract: Methods, apparatus, systems, and articles of manufacture to perform a pseudo-S3 protocol to update firmware and/or activate new firmware with a warm reset are disclosed. An example apparatus includes an advanced configuration and power interface (ACPI) to: initiate a pseudo-sleep event in response to identifying a firmware update; and assert a power button event, the power button event to cause an operating system (OS) to prepare to enter into a sleep state; a basic input/output system (BIOS) to: initiate a warm reset in response to the OS preparing to enter the sleep state, the warm reset to update firmware according to the firmware update; and transmit a wake vector to the OS to continue operation.
-
4.发明公开公开(公告)号：US20230305834A1
公开(公告)日：2023-09-28
申请号：US18040147
申请日：2020-08-25
Applicant: Intel Corporation
Inventor： Mohan Kumar , Sarathy Jayakumar , Brett Peng Wang , Ashok Raj , Murugasamy Nachimuthu
IPC: G06F8/65 , G06F9/4401
CPC classification number: G06F8/65 , G06F9/4418
Abstract: Methods, apparatus, systems, and articles of manufacture to perform a pseudo-S3 protocol to update firmware and/or activate new firmware with a warm reset are disclosed. An example apparatus includes an advanced configuration and power interface (ACPI) to: initiate a pseudo-sleep event in response to identifying a firmware update; and assert a power button event, the power button event to cause an operating system (OS) to prepare to enter into a sleep state; a basic input/output system (BIOS) to: initiate a warm reset in response to the OS preparing to enter the sleep state, the warm reset to update firmware according to the firmware update; and transmit a wake vector to the OS to continue operation.
-
Patent Agency Ranking
公开(公告)号：US20210248026A1
公开(公告)日：2021-08-12
申请号：US17153337
申请日：2021-01-20
Applicant: Intel Corporation
Inventor： Mohan J. Kumar , Theodros Yigzaw , Murugasamy Nachimuthu , Ashok Raj , Jose Vargas
IPC: G06F11/07
Abstract: Techniques and mechanisms for a processor to efficiently identify a circuit resource as being a source of data poisoning. In an embodiment, metadata is communicated, in association with a communication of poisoned data to which the metadata pertains, to a first circuit block of a processor. The metadata indicates a poisoned state of the data, wherein the metadata identifies a second circuit block—which is included in or coupled to the processor—as being a poisoner of the data. Based on the metadata, the first circuit block generates a fault message which identifies the second circuit block as the poisoner of the data. In another embodiment, the processor further comprises the second circuit block, which poisons the data (based on the detection of an error condition) by providing in the metadata a unique identifier which is assigned to the second circuit block.
-
公开(公告)号：US20180150293A1
公开(公告)日：2018-05-31
申请号：US15824604
申请日：2017-11-28
Applicant: Intel Corporation
Inventor： Murugasamy Nachimuthu , Mohan J. Kumar
Abstract: Technologies for lifecycle management include multiple computing devices in communication with a lifecycle management server. On boot, a computing device loads a lightweight firmware boot environment. The lightweight firmware boot environment connects to the lifecycle management server and downloads one or more firmware images for controllers of the computing device. The controllers may include baseboard management controllers, network interface controllers, solid-state drive controllers, or other controllers. The lifecycle management server may select firmware images and/or versions of firmware images based on the controllers or the computing device. The computing device installs each firmware image to a controller memory device coupled to a controller, and in use, each controller accesses the firmware image in the controller memory device. The controller memory device may be a DRAM device or a high-performance byte-addressable non-volatile memory. Other embodiments are described and claimed.
-
公开(公告)号：US20210365559A1
公开(公告)日：2021-11-25
申请号：US17392012
申请日：2021-08-02
Applicant: Intel Corporation
Inventor： Sarathy Jayakumar , Jiewen Yao , Murugasamy Nachimuthu , Ruixia Li , Siyuan Fu , Chuan SONG , Wei Xu
IPC: G06F21/57
Abstract: Methods and apparatus for seamless system management mode (SMM) code injection. A code injection listener is installed in BIOS during booting of the computer system or platform. During operating system (OS) runtime operation a secure execution mode code injection image comprising injected code is received and delivered to the BIOS. The processor execution mode is switched to a secure execution mode such as SMM, and while in the secure execution mode the injected code is accessed and executed on the processor to effect one or more changes such as patching processor microcode, a profile or policy reconfiguration, and a security fix. The solution enables platform changes to be effected during OS runtime without having to reboot the system.
-
公开(公告)号：US11182324B2
公开(公告)日：2021-11-23
申请号：US16905395
申请日：2020-06-18
Applicant: Intel Corporation
Inventor： Mohan Kumar , Murugasamy Nachimuthu
Abstract: Mechanisms for Field Programmable Gate Array (FPGA) chaining and unified FPGA views to a composed system hosts and associated methods, apparatus, systems and software A rack is populated with pooled system drawers including pooled compute drawers and pooled FPGA drawers communicatively coupled via input-output (IO) cables. The FPGA resources in the pooled system drawers are enumerated, identifying a location of type of each FPGA and whether it is a chainable FPGA. Intra-drawer chaining mechanisms are identified for the chainable FPGAs in each pooled compute and pooled FPGA drawer. Inter-drawer chaining mechanism are also identified for chaining FPGAs in separate pooled system drawers. The enumerated FPGA and chaining mechanism data is aggregated to generate a unified system view of the FPGA resources and their chaining mechanisms. Based on available compute nodes and FPGAs in the unified system view, new compute nodes are composed using chained FPGAs. The chained FPGAs are exposed to a hypervisor or operating system virtualization layer, or to an operating system hosted by the composed compute node as a virtual monolithic FPGA or multiple local FPGAs.
-
公开(公告)号：US09015388B2
公开(公告)日：2015-04-21
申请号：US13930643
申请日：2013-06-28
Applicant: Intel Corporation
Inventor： Murugasamy Nachimuthu , Mohan Kumar , Dimitrios Ziakas
CPC classification number: G06F12/1408 , G06F21/575 , G06F21/78
Abstract: In an embodiment, a computing device may include a control unit. The control unit may acquire a request from a central processing unit (CPU), contained in the computing device, that may be executing a basic input/output system (BIOS) associated with the computing device. The request may include a request for a value that may represent a maximum authorized storage size for a storage contained in the computing device. The control unit may generate the value and send the value to the CPU. The CPU may generate a system address map based on the value. The CPU may send the system address map to the control unit which may acquire the system address map and configure an address decoder, contained in the computing device, based on the acquired system address map.
Abstract translation: 在一个实施例中，计算设备可以包括控制单元。 控制单元可以从包含在计算设备中的中央处理单元（CPU）获取可能正在执行与计算设备相关联的基本输入/输出系统（BIOS）的请求。 请求可以包括对可能表示包含在计算设备中的存储的最大授权存储大小的值的请求。 控制单元可以生成值并将值发送到CPU。 CPU可以基于该值生成系统地址映射。 CPU可以将系统地址映射发送到控制单元，控制单元可以基于所获取的系统地址映射来获取系统地址映射并且配置包含在计算设备中的地址解码器。
-
-
-
-
-
-
-
-
Search Results
9
records
(took 0.015 seconds)
