公开(公告)号：US20240311330A1

公开(公告)日：2024-09-19

申请号：US18399463

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Narasimha Lanka ,  Peter Onufryk ,  Swadesh Choudhary ,  Gerald Pasdast ,  Zuoguo Wu ,  Dimitrios Ziakas ,  Sridhar Muthrasanallur

IPC: G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4295 ,  G06F13/1689 ,  G06F2213/0038 ,  G06F2213/0064

Abstract: Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to on-package die-to-die (D2D) interconnects. Specifically, embodiments herein may relate to on-package D2D interconnects for memory that use or relate to the Universal Chiplet Interconnect Express (UCIe) adapter or physical layer (PHY). Other embodiments are described and claimed.

公开(公告)号：US11245604B2

公开(公告)日：2022-02-08

申请号：US16951723

申请日：2020-11-18

Applicant: INTEL CORPORATION

Inventor： Mahesh Wagh ,  Mark S. Myers ,  Stephen R. Van Doren ,  Dimitrios Ziakas ,  Bassam N. Coury

IPC: G06F3/06 ,  G06F13/40 ,  G06F13/16 ,  H04L12/26 ,  G06F16/901 ,  H04B10/25 ,  G02B6/38 ,  G02B6/42 ,  G02B6/44 ,  G06F1/18 ,  G06F1/20 ,  G06F8/65 ,  G06F9/30 ,  G06F9/4401 ,  G06F9/54 ,  G06F12/109 ,  G06F12/14 ,  G08C17/02 ,  G11C5/02 ,  G11C7/10 ,  G11C11/56 ,  G11C14/00 ,  H03M7/30 ,  H03M7/40 ,  H04L12/24 ,  H04L12/931 ,  H04L12/947 ,  H04L29/08 ,  H04L29/06 ,  H04Q11/00 ,  H05K7/14 ,  G06F15/16 ,  G06F9/38 ,  G06F9/50 ,  H04L12/851 ,  H04L12/811 ,  H05K5/02 ,  H04W4/80 ,  G06Q10/08 ,  G06Q10/00 ,  G06Q50/04 ,  H04J14/00 ,  H04L12/911 ,  B25J15/00 ,  B65G1/04 ,  H05K7/20 ,  H04L12/939 ,  H04W4/02 ,  H04L12/751 ,  G06F13/42 ,  H05K1/18 ,  G05D23/19 ,  G05D23/20 ,  H04L12/927 ,  H05K1/02 ,  H04L12/781 ,  H04Q1/04 ,  G06F12/0893 ,  H05K13/04 ,  G11C5/06 ,  G06F11/14 ,  G06F11/34 ,  G06F12/0862 ,  G06F15/80 ,  H04L12/919 ,  G06F12/10 ,  G06Q10/06 ,  G07C5/00 ,  H04L12/28 ,  H04L29/12 ,  H04L9/06 ,  H04L9/14 ,  H04L9/32 ,  H04L12/933

Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to determine a configuration for a plurality of connectors, the configuration to associate a first interconnect protocol with a first subset of the plurality of connectors and a second interconnect protocol with a second subset of the plurality of connectors, the first interconnect protocol and the second interconnect protocol are different interconnect protocols and each comprising one of a serial link protocol, a coherent link protocol, and an accelerator link protocol, cause processing of data for communication via the first subset of the plurality of connectors in accordance with the first interconnect protocol, and cause processing of data for communication via the second subset of the plurality of connector in accordance with the second interconnect protocol.

公开(公告)号：US10211120B2

公开(公告)日：2019-02-19

申请号：US14998123

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Russell S. Aoki ,  Jonathan W. Thibado ,  Jeffory L. Smalley ,  David J. Llapitan ,  Thomas A. Boyd ,  Harvey R. Kofstad ,  Dimitrios Ziakas ,  Hongfei Yan

IPC: H01L23/34 ,  H01L23/498 ,  H05K1/02 ,  H05K1/14 ,  H05K3/34

Abstract: A rework grid array interposer with direct power is described. The interposer has a foundation layer mountable between a motherboard and a package. A heater is embedded in the foundation layer to provide local heat to reflow solder to enable at least one of attachment or detachment of the package. A connector is mounted on the foundation layer and coupled to the heater and to the package to provide a connection path directly with the power supply and not via the motherboard. One type of interposer interfaces with a package having a solderable extension. Another interposer has a plurality of heater zones embedded in the foundation layer.

公开(公告)号：US09832876B2

公开(公告)日：2017-11-28

申请号：US14575775

申请日：2014-12-18

Applicant: INTEL CORPORATION

Inventor： Mani Prakash ,  Thomas T. Holden ,  Jeffory L. Smalley ,  Ram S. Viswanath ,  Bassam N. Coury ,  Dimitrios Ziakas ,  Chong J. Zhao ,  Jonathan W. Thibado ,  Gregorio R. Murtagian ,  Kuang C. Liu ,  Rajasekaran Swaminathan ,  Zhichao Zhang ,  John M. Lynch ,  David J. Llapitan ,  Sanka Ganesan ,  Xiang Li ,  George Vergis

IPC: H05K1/18 ,  H01L23/00 ,  H01R12/71 ,  H01R12/79

CPC classification number: H05K1/181 ,  H01L23/00 ,  H01L23/498 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01R12/712 ,  H01R12/79 ,  H05K2201/10159 ,  H05K2201/10325 ,  Y02P70/611

Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.

公开(公告)号：US10586764B2

公开(公告)日：2020-03-10

申请号：US16072219

申请日：2016-03-31

Applicant: INTEL CORPORATION

Inventor： Russell S. Aoki ,  Dimitrios Ziakas

IPC: H01L23/522 ,  H01L23/498 ,  H01L23/538 ,  H01L23/14 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/34 ,  H01L23/00 ,  H01L23/34

Abstract: Semiconductor packages with programmable routing pathways are disclosed. The semiconductor package may have a source trace that may be electrically coupled to two or more different electrical pathways, where any of the electrical pathways may be activated to provide an electrical connection between the source trace and one or more destination nodes. Each of the electrical pathways may have a corresponding metal well with a correspond airgap overlying the metal well, as well as corresponding heating elements. If a particular heating element is energized, the heating element may melt metal in a corresponding metal well and the molten metal may migrate by capillary action into the overlying airgap to complete an electrical connection between the source trace and a destination node.

公开(公告)号：US10581596B2

公开(公告)日：2020-03-03

申请号：US15859367

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Mark Schmisseur ,  Dimitrios Ziakas ,  Murugasamy K. Nachimuthu

IPC: G06F11/00 ,  H04L9/08 ,  G06F3/06 ,  G06F9/50 ,  H04L29/06 ,  H04L29/08 ,  G06F16/25 ,  G06F16/2453 ,  H04L12/861 ,  G11C8/12 ,  G11C29/02 ,  H04L12/24 ,  G11C29/36 ,  G11C29/38 ,  G11C29/44 ,  G06F16/22 ,  G06F16/2455 ,  G06F12/02 ,  G06F12/14 ,  G06F13/16 ,  G06F15/173 ,  G06F13/40 ,  G06F13/42 ,  G06F9/448 ,  G06F9/28 ,  G06F15/16 ,  H04L12/703 ,  H04L12/743 ,  H04L12/801 ,  H04L12/803 ,  H04L12/935 ,  H04L12/931 ,  G06F9/4401 ,  G06F9/445 ,  G06F12/06 ,  G06F16/23 ,  G06F16/248 ,  G06F16/901 ,  G06F16/11 ,  G06F12/0802 ,  G06F12/1045

Abstract: Technologies for managing errors in a remotely accessible memory pool include a memory sled. The memory sled includes a memory pool having one or more byte-addressable memory devices and a memory pool controller coupled to the memory pool. The memory sled is to write test data to a byte-addressable memory region in the memory pool. The memory region is to be accessed by a remote compute sled. The memory sled is also to read data from the memory region to which the test data was written, compare the read data to the test data to determine whether a threshold number of errors are present in the read data, and send, in response to a determination that the threshold number of errors are present in the read data, a notification to the remote compute sled that the memory region is faulty.

公开(公告)号：US20190042408A1

公开(公告)日：2019-02-07

申请号：US15868492

申请日：2018-01-11

Applicant: Intel Corporation

Inventor： Mark Schmisseur ,  Dimitrios Ziakas ,  Murugasamy K. Nachimuthu

IPC: G06F12/06 ,  G06F3/06

Abstract: Technologies for interleaving memory that is accessible via a shared memory pool include a memory sled. The memory sled includes a memory pool of byte-addressable memory devices. The memory sled also includes a memory pool controller coupled to the memory pool. The memory pool controller receives a request to allocate memory addresses of the memory pool to a compute sled. The memory pool controller determines an interleaving configuration for the compute sled as a function of memory characteristics of the compute sled and configures the memory addresses according to the determined interleaving configuration.

公开(公告)号：US10176108B2

公开(公告)日：2019-01-08

申请号：US15283065

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Murugasamy K. Nachimuthu ,  Mohan J. Kumar ,  Dimitrios Ziakas

IPC: G06F12/10 ,  G06F12/06

Abstract: Provided are a method, apparatus, and a system in which an initiator node is configured to communicate with a target node that is coupled to a memory. At system initialization time, a memory address map of the initiator node is generated to include addresses corresponding to the memory to which the target node is coupled. The initiator node accesses the memory coupled to the target node, by using the memory address map of the initiator node.

公开(公告)号：US10884195B2

公开(公告)日：2021-01-05

申请号：US15396501

申请日：2016-12-31

Applicant: INTEL CORPORATION

Inventor： Mahesh Wagh ,  Mark S. Myers ,  Stephen R. Van Doren ,  Dimitrios Ziakas ,  Bassam Coury

IPC: H03M7/40 ,  G02B6/38 ,  G02B6/42 ,  G02B6/44 ,  G06F16/901 ,  H04B10/25 ,  G06F3/06 ,  G11C5/02 ,  G11C14/00 ,  H04L12/24 ,  H04L12/26 ,  H04Q11/00 ,  G06F1/20 ,  H04W4/80 ,  G06F1/18 ,  G06F8/65 ,  G06F9/30 ,  G06F9/38 ,  G06F9/4401 ,  G06F9/50 ,  G06F9/54 ,  G06F12/109 ,  G06F12/14 ,  G06F13/16 ,  G06F13/40 ,  G06Q10/08 ,  G06Q10/00 ,  G06Q50/04 ,  G08C17/02 ,  G11C7/10 ,  G11C11/56 ,  H03M7/30 ,  H04L12/851 ,  H04L12/811 ,  H04L12/931 ,  H04L29/08 ,  H04L29/06 ,  H05K5/02 ,  H05K7/14 ,  H04L12/911 ,  B25J15/00 ,  B65G1/04 ,  H05K7/20 ,  H04L12/939 ,  H04W4/02 ,  H04L12/751 ,  G06F13/42 ,  H05K1/18 ,  G05D23/19 ,  G05D23/20 ,  H04L12/927 ,  H05K1/02 ,  H04L12/781 ,  H04Q1/04 ,  G06F12/0893 ,  H05K13/04 ,  G11C5/06 ,  G06F11/14 ,  G06F11/34 ,  G06F12/0862 ,  G06F15/80 ,  H04L12/919 ,  G06F12/10 ,  G06Q10/06 ,  G07C5/00 ,  H04L12/28 ,  H04L29/12 ,  H04L9/06 ,  H04L9/14 ,  H04L9/32 ,  H04L12/933 ,  H04L12/947

Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to determine a configuration for a plurality of connectors, the configuration to associate a first interconnect protocol with a first subset of the plurality of connectors and a second interconnect protocol with a second subset of the plurality of connectors, the first interconnect protocol and the second interconnect protocol are different interconnect protocols and each comprising one of a serial link protocol, a coherent link protocol, and an accelerator link protocol, cause processing of data for communication via the first subset of the plurality of connectors in accordance with the first interconnect protocol, and cause processing of data for communication via the second subset of the plurality of connector in accordance with the second interconnect protocol.

公开(公告)号：US10476670B2

公开(公告)日：2019-11-12

申请号：US15859369

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Mark Schmisseur ,  Dimitrios Ziakas ,  Murugasamy K. Nachimuthu

IPC: G06F3/06 ,  H04L9/08 ,  G11C29/36 ,  G11C29/38 ,  G11C29/44 ,  G06F16/22 ,  G06F16/2455 ,  G06F12/02 ,  G06F12/14 ,  G06F13/16 ,  G06F15/173 ,  G06F13/40 ,  G06F13/42 ,  G06F9/448 ,  G06F9/28 ,  G06F15/16 ,  H04L12/24 ,  H04L29/06 ,  H04L29/08 ,  H04L12/703 ,  H04L12/743 ,  H04L12/801 ,  H04L12/803 ,  H04L12/935 ,  H04L12/931 ,  G06F9/4401 ,  G06F9/445 ,  G06F12/06 ,  G06F16/23 ,  G06F16/248 ,  G06F16/901 ,  G06F9/50 ,  G06F16/25 ,  G06F16/2453 ,  G06F16/11 ,  H04L12/861 ,  G11C8/12 ,  G11C29/02 ,  G06F12/0802 ,  G06F12/1045

Abstract: Technologies for providing remote access to a shared memory pool include a memory sled. The memory sled includes a memory pool having one or more byte-addressable memory devices and a memory pool controller coupled to the memory pool. The memory pool controller is to produce, for each of a plurality of compute sleds, address space data indicative of addresses of byte-addressable memory in the memory pool accessible to the compute sled, and corresponding permissions associated with the addresses. The memory pool controller is also to provide the address space data to each corresponding compute sled and receive, from a requesting compute sled of the plurality of compute sleds, a memory access request. The memory access request includes an address from the address space data to be accessed. The memory pool controller is also to perform, in response to receiving the memory access request, a memory access operation on the memory pool. Other embodiments are also described and claimed.