公开(公告)号：US20170148868A1

公开(公告)日：2017-05-25

申请号：US15425596

申请日：2017-02-06

Applicant: INTEL CORPORATION

Inventor： NICK LINDERT ,  JOSEPH M. STEIGERWALD ,  KANWAL JIT SINGH

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/75 ,  H01L23/5223 ,  H01L23/53238 ,  H01L27/10808 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/55 ,  H01L28/87 ,  H01L28/90 ,  H01L28/91 ,  H01L2924/0002 ,  H05K1/182 ,  H01L2924/00

Abstract: Techniques are disclosed for integrating capacitors among the metal interconnect for embedded DRAM applications. In some embodiments, the technique uses a wet etch to completely remove the interconnect metal (e.g., copper) that is exposed prior to the capacitor formation. This interconnect metal removal precludes that metal from contaminating the hi-k dielectric of the capacitor. Another benefit is increased height (surface area) of the capacitor, which allows for increased charge storage. In one example embodiment, an integrated circuit device is provided that includes a substrate having at least a portion of a DRAM bit cell circuitry, an interconnect layer on the substrate and including one or more metal-containing interconnect features, and a capacitor at least partly in the interconnect layer and occupying space from which a metal-containing interconnect feature was removed. The integrated circuit device can be, for example, a processor or a communications device.

公开(公告)号：US20160240534A1

公开(公告)日：2016-08-18

申请号：US15024258

申请日：2013-12-18

Applicant: INTEL CORPORATION

Inventor： ANAND S. MURTHY ,  NICK LINDERT ,  GLENN A. GLASS

IPC: H01L27/092 ,  H01L21/265 ,  H01L29/40 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/092 ,  H01L21/26506 ,  H01L21/3065 ,  H01L21/823814 ,  H01L29/0673 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/785 ,  H01L29/78621 ,  H01L29/78696

Abstract: Techniques are disclosed for improving gate control over the channel of a transistor, by increasing the effective electrical gate length (Leff) through deposition of a gate control layer (GCL) at the interfaces of the channel with the source and drain regions. The GCL is a nominally undoped layer (or substantially lower doped layer, relative to the heavily doped S/D fill material) that can be deposited when forming a transistor using replacement S/D deposition. The GCL can be selectively deposited in the S/D cavities after such cavities have been formed and before the heavily doped S/D fill material is deposited. In this manner, the GCL decreases the source and drain underlap (Xud) with the gate stack and further separates the heavily doped source and drain regions. This, in turn, increases the effective electrical gate length (Leff) and improves the control that the gate has over the channel.

Abstract translation: 公开了通过在沟道与源极和漏极区的界面处沉积栅极控制层（GCL）来增加有效电栅极长度（Leff）来改善晶体管的沟道上的栅极控制的技术。 GCL是在使用替换S / D沉积形成晶体管时可以沉积的名义上未掺杂的层（或相对于重掺杂的S / D填充材料的基本上较低的掺杂层）。 在形成这种空穴之后并且沉积重掺杂的S / D填充材料之前，可以将GCL选择性地沉积在S / D腔中。 以这种方式，GCL通过栅极堆叠减少源极和漏极底层（Xud），并进一步分离重掺杂的源极和漏极区域。 这又增加了有效电门长度（Leff），并且改善了栅极通过通道的控制。