公开(公告)号：US20180090185A1

公开(公告)日：2018-03-29

申请号：US15278802

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： MD Altaf HOSSAIN ,  Nagi ABOULENEIN ,  Jayapratap BHARATHAN

IPC: G11C7/10 ,  G06F13/16 ,  G11C8/18

CPC classification number: G11C7/1072 ,  G06F13/1684 ,  G11C5/04 ,  G11C7/1012 ,  G11C8/18

Abstract: A shared command/address (C/A) bus for memory devices in a multi-channel configuration can enable reducing the number of pins and signal lines in a memory subsystem. In one embodiment, a memory controller includes hardware logic to generate commands to access a plurality of memory devices via a plurality of channels and input/output (I/O) circuitry to transmit command/address (C/A) information for the commands to the plurality of memory devices over a single C/A bus for the plurality of channels. In one embodiment, double-speed strobe signal lines can also enable reducing the number of pins and signal lines in a memory subsystem.

公开(公告)号：US20180254079A1

公开(公告)日：2018-09-06

申请号：US15911068

申请日：2018-03-02

Applicant: Intel Corporation

Inventor： Christopher E. COX ,  Uksong KANG ,  Nagi ABOULENEIN

IPC: G11C11/408 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52

Abstract: A multi-die memory device having fixed bandwidth interfaces can selectively connect portions of the interfaces of the multiple memory dies as a memory channel for the multi-die device. The selective application of the interface bits of the memory dies enables the application of ECC (error checking and correction) in memory devices that otherwise have insufficient connectors to exchange ECC information. The device includes circuitry to selectively apply CAS (column address select) signals to the memory dies to selectively connect the connectors of the memory dies. CAS selection can provide various configurations in which selected bits of a first memory die interface are combined with selected bit or bits of a second memory die interface to provide the device interface. The memory dies can operate in byte mode to apply only half of their data I/O (input/output) interface, with CAS doubled up to provide access to the memory arrays.

公开(公告)号：US20190332469A1

公开(公告)日：2019-10-31

申请号：US16504199

申请日：2019-07-05

Applicant: INTEL CORPORATION

Inventor： Amir A. RADJAI ,  Nagi ABOULENEIN ,  Steve L. GEIGER ,  Satyajit A. JADHAV ,  Bezan J. KAPADIA ,  Vivek KOZHIKKOTTU ,  Rashmi LAKKUR SUBRAMANYAM ,  Srithar RAMESH ,  James M. SHEHADI ,  Jason D. VAN DYKEN

IPC: G06F11/10 ,  G06F13/16 ,  G06F9/38 ,  G06F9/54

Abstract: An in-band error correcting code (ECC) module intercepts input/output (I/O) operations directed to a memory. The in-band ECC module determines whether the I/O is directed to data that needs to be protected against error. In response to determining that the I/O is directed to data that needs to be protected against error, the in-band ECC module directs a memory controller to store or access ECC data corresponding to the data in a first preassigned area of the memory, and to store or access the data in a second preassigned area of the memory.