公开(公告)号：US20230418617A1

公开(公告)日：2023-12-28

申请号：US18339454

申请日：2023-06-22

Applicant: INTEL CORPORATION

Inventor： Christopher J. HUGHES ,  Prasoonkumar SURTI ,  Guei-Yuan LUEH ,  Adam T. LAKE ,  Jill BOYCE ,  Subramaniam MAIYURAN ,  Lidong XU ,  James M. HOLLAND ,  Vasanth RANGANATHAN ,  Nikos KABURLASOS ,  Altug KOKER ,  Abhishek R. Appu

IPC: G06F9/38 ,  G06F12/084 ,  G06T1/60 ,  G06F9/50 ,  G06F9/54

CPC classification number: G06F9/3891 ,  G06F12/084 ,  G06T1/60 ,  G06F9/5066 ,  G06F9/544

Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.

公开(公告)号：US20240310889A1

公开(公告)日：2024-09-19

申请号：US18575238

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Nikos KABURLASOS

IPC: G06F1/26 ,  G06F1/3212 ,  G06F1/3215 ,  G06F1/3234

CPC classification number: G06F1/263 ,  G06F1/3212 ,  G06F1/3215 ,  G06F1/3234

Abstract: An apparatus for managing a power consumption of processor or memory circuitry comprising a plurality of processing or memory functional units may be provided. The processor or memory circuitry is arranged to receive electrical power from an alternating current, AC, power source or a battery. The apparatus comprises processing circuitry to: based on an indication that the processor or memory circuitry is receiving electrical power from the AC power source, selectively cause operational electrical power to be provided to a first number of the functional units of the processor or memory circuitry. The processing circuitry is further to: based on an indication that the circuitry is receiving electrical power from the battery, selectively cause operational electrical power to be provided to a second number of the functional units of the processor or memory circuitry, the second number being less than the first number.

公开(公告)号：US20210149680A1

公开(公告)日：2021-05-20

申请号：US17095585

申请日：2020-11-11

Applicant: Intel Corporation

Inventor： Christopher J. HUGHES ,  Prasoonkumar SURTI ,  Guei-Yuan LUEH ,  Adam T. LAKE ,  Jill BOYCE ,  Subramaniam MAIYURAN ,  Lidong XU ,  James M. HOLLAND ,  Vasanth RANGANATHAN ,  Nikos KABURLASOS ,  Altug KOKER ,  Abhishek R. APPU

IPC: G06F9/38 ,  G06F12/084 ,  G06F9/54 ,  G06F9/50 ,  G06T1/60

Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.

公开(公告)号：US20200311860A1

公开(公告)日：2020-10-01

申请号：US16369608

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Nikos KABURLASOS ,  Eric SAMSON ,  Jaymin B. JASOLIYA

IPC: G06T1/20 ,  G06F9/30 ,  G06F1/3234 ,  G06F1/3228 ,  G06F1/3296

Abstract: Described is an apparatus comprising a first circuitry and a second circuitry. The first circuitry may process a sequence of Graphics Processing Unit (GPU) commands including an instruction carrying a flag that indicates a workload characteristic corresponding with the sequence of GPU commands. The second circuitry may initiate a power-directed parameter adjustment based upon the flag.