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公开(公告)号：US11315304B2
公开(公告)日：2022-04-26
申请号：US17003011
申请日：2020-08-26
Applicant: INTEL CORPORATION
Inventor： Scott Janus , Prasoonkumar Surti , Karthik Vaidyanathan , Alexey Supikov , Gabor Liktor , Carsten Benthin , Philip Laws , Michael Doyle
Abstract: Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.
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公开(公告)号：US11069123B2
公开(公告)日：2021-07-20
申请号：US16236218
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Carson Brownlee , Joshua Barczak , Kai Xiao , Michael Apodaca , Philip Laws , Thomas Raoux , Travis Schluessler
Abstract: Cloud-based real time rendering. For example, one embodiment of a system comprises: a first graphics processing node to perform a first set of graphics processing operations to render a graphics scene, the first set of graphics processing operations comprising ray-tracing independent operations; an interconnect or network interface coupling the first graphics processing node to a second graphics processing node; the second graphics processing node to receive an indication of a current view of a user of the first graphics processing node and to receive or construct a view-independent surface generated by view-independent ray traversal and intersection operations; the second graphics processing node to responsively perform a view-dependent translation of the view-independent surface based on the current view of the user to generate a view-dependent surface and to provide the view-dependent surface to the first graphics processing node; and the first graphics processing node to perform a second set of graphics processing operations to complete rendering of the graphics scene using the view-dependent surface.
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公开(公告)号：US10929948B2
公开(公告)日：2021-02-23
申请号：US16236110
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Carsten Benthin , Prasoonkumar Surti , Karthik Vaidyanathan , Philip Laws , Scott Janus
IPC: G06T1/60 , G06T1/20 , G06F12/0862
Abstract: An apparatus and method for hardware page cache migration. For example, one embodiment of an apparatus comprises: a memory management unit (MMU) to manage memory page migration in multi-processor environments in which multiple processors share a virtual memory address space, the memory page migration comprising movement of one or more memory pages from a local memory of a first processor to a local memory of a second processor; a central page cache integral to or coupled to the MMU, the central page cache to store memory pages based on requests generated from one or more of the multiple processors; access pattern detection circuitry/logic to detect data access patterns associated with data access requests from one or more of the multiple processors; and an adaptive page prefetcher to prefetch one or more memory pages to the central page cache responsive to the access pattern detection circuitry/logic detecting one of the data access patterns.
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公开(公告)号：US20200211152A1
公开(公告)日：2020-07-02
申请号：US16236110
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Carsten Benthin , Prasoonkumar Surti , Karthik Vaidyanathan , Philip Laws , Scott Janus
IPC: G06T1/60 , G06T1/20 , G06F12/0862
Abstract: An apparatus and method for hardware page cache migration. For example, one embodiment of an apparatus comprises: a memory management unit (MMU) to manage memory page migration in multi-processor environments in which multiple processors share a virtual memory address space, the memory page migration comprising movement of one or more memory pages from a local memory of a first processor to a local memory of a second processor; a central page cache integral to or coupled to the MMU, the central page cache to store memory pages based on requests generated from one or more of the multiple processors; access pattern detection circuitry/logic to detect data access patterns associated with data access requests from one or more of the multiple processors; and an adaptive page prefetcher to prefetch one or more memory pages to the central page cache responsive to the access pattern detection circuitry/logic detecting one of the data access patterns.
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公开(公告)号：US11989815B2
公开(公告)日：2024-05-21
申请号：US17677118
申请日：2022-02-22
Applicant: INTEL CORPORATION
Inventor： Prasoonkumar Surti , Carsten Benthin , Karthik Vaidyanathan , Philip Laws , Scott Janus , Sven Woop
CPC classification number: G06T15/005 , G06T1/20 , G06T15/06 , G06T2210/52
Abstract: Cluster of acceleration engines to accelerate intersections. For example, one embodiment of an apparatus comprises: a set of graphics cores to execute a first set of instructions of a primary graphics thread; a scalar cluster comprising a plurality of scalar execution engines; and a communication fabric interconnecting the set of graphics cores and the scalar cluster; the set of graphics cores to offload execution of a second set of instructions associated with ray traversal and/or intersection operations to the scalar cluster; the scalar cluster comprising a plurality of local memories, each local memory associated with one of the scalar execution engines, wherein each local memory is to store a portion of a hierarchical acceleration data structure required by an associated scalar execution engine to execute one or more of the second set of instructions; the plurality of scalar execution engines to store results of the execution of the second set of instructions in a memory accessible by the set of graphics cores; wherein the set of graphics cores are to process the results within the primary graphics thread.
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Patent Agency Ranking
公开(公告)号：US11062500B2
公开(公告)日：2021-07-13
申请号：US16236041
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Scott Janus , Prasoonkumar Surti , Karthik Vaidyanathan , Carsten Benthin , Philip Laws
Abstract: Apparatus and method for ray tracing acceleration using a grid primitive. For example, one embodiment of an apparatus comprises: a grid primitive generator to generate a grid primitive comprising a plurality of adjacent interconnected primitives; a bitmask generator to generate a bitmask associated with the grid primitive, the bitmask comprising a plurality of bitmask values, each mask value associated with a primitive of the grid primitive; a ray tracing engine comprising traversal and intersection hardware logic to perform traversal and intersection operations in which rays are traversed through a hierarchical acceleration data structure and intersections between the rays and one or more of the adjacent interconnected primitives identified, wherein the ray tracing engine is to read the bitmask to determine a first set of primitives from the grid primitive on which to perform the traversal and intersection operations and a second set of primitives from the grid primitive on which the traversal and intersection operations will not be performed.
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公开(公告)号：US11880928B2
公开(公告)日：2024-01-23
申请号：US17723772
申请日：2022-04-19
Applicant: INTEL CORPORATION
Inventor： Scott Janus , Prasoonkumar Surti , Karthik Vaidyanathan , Alexey Supikov , Gabor Liktor , Carsten Benthin , Philip Laws , Michael Doyle
CPC classification number: G06T15/06 , G06T1/60 , G06T15/005 , G06T17/005 , G06T2210/21
Abstract: Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.
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公开(公告)号：US11263799B2
公开(公告)日：2022-03-01
申请号：US16910434
申请日：2020-06-24
Applicant: INTEL CORPORATION
Inventor： Prasoonkumar Surti , Carsten Benthin , Karthik Vaidyanathan , Philip Laws , Scott Janus , Sven Woop
Abstract: Cluster of acceleration engines to accelerate intersections. For example, one embodiment of an apparatus comprises: a set of graphics cores to execute a first set of instructions of a primary graphics thread; a scalar cluster comprising a plurality of scalar execution engines; and a communication fabric interconnecting the set of graphics cores and the scalar cluster; the set of graphics cores to offload execution of a second set of instructions associated with ray traversal and/or intersection operations to the scalar cluster; the scalar cluster comprising a plurality of local memories, each local memory associated with one of the scalar execution engines, wherein each local memory is to store a portion of a hierarchical acceleration data structure required by an associated scalar execution engine to execute one or more of the second set of instructions; the plurality of scalar execution engines to store results of the execution of the second set of instructions in a memory accessible by the set of graphics cores; wherein the set of graphics cores are to process the results within the primary graphics thread.
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公开(公告)号：US10930051B2
公开(公告)日：2021-02-23
申请号：US16235744
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Scott Janus , Prasoonkumar Surti , Karthik Vaidyanathan , Gabor Liktor , Carsten Benthin , Philip Laws
Abstract: Apparatus and method for general ray tracing queries. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes associated with a graphics scene; traversal/intersection hardware logic to traverse one or more rays through the acceleration data structure to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; shape processing hardware logic to specify three dimensional (3D) shape data indicating one or more 3D shapes to be used to perform queries with respect to the hierarchical acceleration data structure; query processing hardware logic to execute queries comprising comparisons between nodes of the hierarchical acceleration data structure and the 3D shape data to generate a result indicating overlap between the 3D shapes and the nodes.
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公开(公告)号：US10762686B2
公开(公告)日：2020-09-01
申请号：US16235906
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Scott Janus , Prasoonkumar Surti , Karthik Vaidyanathan , Alexey Supikov , Gabor Liktor , Carsten Benthin , Philip Laws , Michael Doyle
Abstract: Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.
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