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公开(公告)号：US10957095B2
公开(公告)日：2021-03-23
申请号：US16056222
申请日：2018-08-06
Applicant: Intel Corporation
Inventor： Karthik Vaidyanathan , Won-Jong Lee , Gabor Liktor , John G. Gierach , Pawel Majewski , Prasoonkumar Surti , Carsten Benthin , Sven Woop , Thomas Raoux
Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.
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公开(公告)号：US11069123B2
公开(公告)日：2021-07-20
申请号：US16236218
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Carson Brownlee , Joshua Barczak , Kai Xiao , Michael Apodaca , Philip Laws , Thomas Raoux , Travis Schluessler
Abstract: Cloud-based real time rendering. For example, one embodiment of a system comprises: a first graphics processing node to perform a first set of graphics processing operations to render a graphics scene, the first set of graphics processing operations comprising ray-tracing independent operations; an interconnect or network interface coupling the first graphics processing node to a second graphics processing node; the second graphics processing node to receive an indication of a current view of a user of the first graphics processing node and to receive or construct a view-independent surface generated by view-independent ray traversal and intersection operations; the second graphics processing node to responsively perform a view-dependent translation of the view-independent surface based on the current view of the user to generate a view-dependent surface and to provide the view-dependent surface to the first graphics processing node; and the first graphics processing node to perform a second set of graphics processing operations to complete rendering of the graphics scene using the view-dependent surface.
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公开(公告)号：US10762668B2
公开(公告)日：2020-09-01
申请号：US16235672
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Carson Brownlee , Carsten Benthin , Joshua Barczak , Kai Xiao , Michael Apodaca , Prasoonkumar Surti , Thomas Raoux
Abstract: Apparatus and method for context-aware compression. For example, one embodiment of an apparatus comprises: ray traversal/intersection circuitry to traverse rays through a hierarchical acceleration data structure to identify intersections between rays and primitives of a graphics scene; matrix compression circuitry/logic to compress hierarchical transformation matrices to generate compressed hierarchical transformation matrices by quantizing N-bit floating point data elements associated with child transforms of the hierarchical transformation matrices to variable-bit floating point numbers or integers comprising offsets from a parent transform of the child transform; and an instance processor to generate a plurality of instances of one or more base geometric objects in accordance with the compressed hierarchical transformation matrices.
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公开(公告)号：US10748323B2
公开(公告)日：2020-08-18
申请号：US16208632
申请日：2018-12-04
Applicant: Intel Corporation
Inventor： John Gierach , Srividya Karumuri , Thomas Raoux , Devan Burke , Wojtek Rajski , Jeremy Brennan
Abstract: Embodiments described herein provide a general purpose graphics processing device, comprising a general purpose graphics processing compute block to process a workload including graphics or compute operations, a memory, and a constant folding unit comprising a processing unit to receive a first input shader and metadata for the first input shader, receive a first constant buffer comprising runtime constants for the first input shader, and generate an improved shader from the first input shader and the runtime constants. Other embodiments may be described and claimed.
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公开(公告)号：US12236519B2
公开(公告)日：2025-02-25
申请号：US18090810
申请日：2022-12-29
Applicant: INTEL CORPORATION
Inventor： Karthik Vaidyanathan , Michael Apodaca , Thomas Raoux , Carsten Benthin , Kai Xiao , Carson Brownlee , Joshua Barczak
Abstract: An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.
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Patent Agency Ranking
公开(公告)号：US11461954B2
公开(公告)日：2022-10-04
申请号：US17223464
申请日：2021-04-06
Applicant: Intel Corporation
Inventor： Michael Apodaca , John Feit , David Cimini , Thomas Raoux , Konstantin Levit-Gurevich
IPC: G06T15/00
Abstract: An apparatus to facilitate an update of shader data constants. The apparatus includes one or more processors to detect a change to one or more data constants in a shader program, generate a micro-code block including updated constants data during execution of the shader program and transmit the micro-code block to the shader program.
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公开(公告)号：US20210225062A1
公开(公告)日：2021-07-22
申请号：US17223464
申请日：2021-04-06
Applicant: Intel Corporation
Inventor： Michael Apodaca , John Feit , David Cimini , Thomas Raoux , Konstantin Levit-Gurevich
IPC: G06T15/00
Abstract: An apparatus to facilitate an update of shader data constants. The apparatus includes one or more processors to detect a change to one or more data constants in a shader program, generate a micro-code block including updated constants data during execution of the shader program and transmit the micro-code block to the shader program.
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公开(公告)号：US11915459B2
公开(公告)日：2024-02-27
申请号：US17740754
申请日：2022-05-10
Applicant: INTEL CORPORATION
Inventor： Carson Brownlee , Carsten Benthin , Joshua Barczak , Kai Xiao , Michael Apodaca , Prasoonkumar Surti , Thomas Raoux
CPC classification number: G06T9/40 , G06T1/60 , G06T15/06 , G06T15/20 , G06T2210/21
Abstract: Apparatus and method for context-aware compression. For example, one embodiment of an apparatus comprises: ray traversal/intersection circuitry to traverse rays through a hierarchical acceleration data structure to identify intersections between rays and primitives of a graphics scene; matrix compression circuitry/logic to compress hierarchical transformation matrices to generate compressed hierarchical transformation matrices by quantizing N-bit floating point data elements associated with child transforms of the hierarchical transformation matrices to variable-bit floating point numbers or integers comprising offsets from a parent transform of the child transform; and an instance processor to generate a plurality of instances of one or more base geometric objects in accordance with the compressed hierarchical transformation matrices.
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公开(公告)号：US11568591B2
公开(公告)日：2023-01-31
申请号：US16996208
申请日：2020-08-18
Applicant: INTEL CORPORATION
Inventor： Karthik Vaidyanathan , Michael Apodaca , Thomas Raoux , Carsten Benthin , Kai Xiao , Carson Brownlee , Joshua Barczak
Abstract: An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.
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公开(公告)号：US11158111B2
公开(公告)日：2021-10-26
申请号：US16915599
申请日：2020-06-29
Applicant: Intel Corporation
Inventor： Kai Xiao , Michael Apodaca , Carson Brownlee , Thomas Raoux , Joshua Barczak , Gabor Liktor
Abstract: Apparatus and method for bottom-up BVH refit. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes; traversal hardware logic to traverse one or more rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node unit comprising circuitry and/or logic to perform refit operations on nodes of the hierarchical acceleration data structure, the refit operations to adjust spatial dimensions of one or more of the nodes; and an early termination evaluator to determine whether to proceed with refit operations or to terminate refit operations for a current node based on refit data associated with one or more child nodes of the current node.
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