公开(公告)号：US20170162661A1

公开(公告)日：2017-06-08

申请号：US15436336

申请日：2017-02-17

Applicant: INTEL CORPORATION

Inventor： MICHAEL G. HAVERTY ,  SADASIVAN SHANKAR ,  TAHIR GHANI ,  SEONGJUN PARK

IPC: H01L29/417 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/283 ,  H01L21/3205 ,  H01L23/482 ,  H01L23/485 ,  H01L29/0895 ,  H01L29/456 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques are disclosed for forming contacts in silicon semiconductor devices. In some embodiments, a transition layer forms a non-reactive interface with the silicon semiconductor contact surface. In some such cases, a conductive material provides the contacts and the material forming a non-reactive interface with the silicon surface. In other cases, a thin semiconducting or insulating layer provides the non-reactive interface with the silicon surface and is coupled to conductive material of the contacts. The techniques can be embodied, for instance, in planar or non-planar (e.g., double-gate and tri-gate FinFETs) transistor devices.

公开(公告)号：US20160043191A1

公开(公告)日：2016-02-11

申请号：US14886778

申请日：2015-10-19

Applicant: INTEL CORPORATION

Inventor： MICHAEL G. HAVERTY ,  SADASIVAN SHANKAR ,  TAHIR GHANI ,  SEONGJUN PARK

IPC: H01L29/417 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/283 ,  H01L21/3205 ,  H01L23/482 ,  H01L23/485 ,  H01L29/0895 ,  H01L29/456 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques are disclosed for forming contacts in silicon semiconductor devices. In some embodiments, a transition layer forms a non-reactive interface with the silicon semiconductor contact surface. In some such cases, a conductive material provides the contacts and the material forming a non-reactive interface with the silicon surface. In other cases, a thin semiconducting or insulating layer provides the non-reactive interface with the silicon surface and is coupled to conductive material of the contacts. The techniques can be embodied, for instance, in planar or non-planar (e.g., double-gate and tri-gate FinFETs) transistor devices.

Abstract translation: 公开了用于在硅半导体器件中形成接触的技术。 在一些实施例中，过渡层与硅半导体接触表面形成非反应性界面。 在一些这种情况下，导电材料提供触点和与硅表面形成非反应性界面的材料。 在其他情况下，薄的半导体或绝缘层提供与硅表面的非反应性界面并且耦合到触点的导电材料。 这些技术可以例如在平面或非平面（例如，双栅极和三栅极FinFET））晶体管器件中实现。