公开(公告)号：US10372668B2

公开(公告)日：2019-08-06

申请号：US15870632

申请日：2018-01-12

Applicant: INTEL CORPORATION

Inventor： Chang Yong Kang ,  Pierre Laurent ,  Hari K. Tadepalli ,  Prasad M. Ghatigar ,  T.J. O'Dwyer ,  Serge Zhilyaev

IPC: G06F15/80 ,  G06F13/16 ,  G06F13/36 ,  G06F13/40 ,  G06F9/312 ,  G06F9/38 ,  G06F9/30

Abstract: Methods and apparatuses relating to tightly-coupled heterogeneous computing are described. In one embodiment, a hardware processor includes a plurality of execution units in parallel, a switch to connect inputs of the plurality of execution units to outputs of a first buffer and a plurality of memory banks and connect inputs of the plurality of memory banks and a plurality of second buffers in parallel to outputs of the first buffer, the plurality of memory banks, and the plurality of execution units, and an offload engine with inputs connected to outputs of the plurality of second buffers.

公开(公告)号：US20180225255A1

公开(公告)日：2018-08-09

申请号：US15870632

申请日：2018-01-12

Applicant: INTEL CORPORATION

Inventor： Chang Yong Kang ,  Pierre Laurent ,  Hari K. Tadepalli ,  Prasad M. Ghatigar ,  T.J. O'Dwyer ,  Serge Zhilyaev

IPC: G06F15/80 ,  G06F9/38 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F15/8061 ,  G06F9/30036 ,  G06F9/3814 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3877 ,  G06F13/16 ,  G06F13/4059 ,  G06F15/8007 ,  G06F15/8084

Abstract: Methods and apparatuses relating to tightly-coupled heterogeneous computing are described. In one embodiment, a hardware processor includes a plurality of execution units in parallel, a switch to connect inputs of the plurality of execution units to outputs of a first buffer and a plurality of memory banks and connect inputs of the plurality of memory banks and a plurality of second buffers in parallel to outputs of the first buffer, the plurality of memory banks, and the plurality of execution units, and an offload engine with inputs connected to outputs of the plurality of second buffers.

公开(公告)号：US20160378715A1

公开(公告)日：2016-12-29

申请号：US14752047

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Chang Yong Kang ,  Pierre Laurent ,  Hari K. Tadepalli ,  Prasad M. Ghatigar ,  T.J. O'Dwyer ,  Serge Zhilyaev

IPC: G06F15/80

CPC classification number: G06F15/8061 ,  G06F9/30036 ,  G06F9/3814 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3877 ,  G06F13/16 ,  G06F13/4059

Abstract: Methods and apparatuses relating to tightly-coupled heterogeneous computing are described. In one embodiment, a hardware processor includes a plurality of execution units in parallel, a switch to connect inputs of the plurality of execution units to outputs of a first buffer and a plurality of memory banks and connect inputs of the plurality of memory banks and a plurality of second buffers in parallel to outputs of the first buffer, the plurality of memory banks, and the plurality of execution units, and an offload engine with inputs connected to outputs of the plurality of second buffers.

Abstract translation: 描述了与紧耦合异构计算有关的方法和设备。 在一个实施例中，硬件处理器并行地包括多个执行单元，用于将多个执行单元的输入连接到第一缓冲器和多个存储器组的输出并连接多个存储体的输入的开关和 与第一缓冲器，多个存储体和多个执行单元的输出并联的多个第二缓冲器，以及具有连接到多个第二缓冲器的输出的输入的卸载引擎。

公开(公告)号：US09870339B2

公开(公告)日：2018-01-16

申请号：US14752047

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Chang Yong Kang ,  Pierre Laurent ,  Hari K. Tadepalli ,  Prasad M. Ghatigar ,  T. J. O'Dwyer ,  Serge Zhilyaev

IPC: G06F15/76 ,  G06F13/36 ,  G06F15/80 ,  G06F13/16 ,  G06F13/40 ,  G06F9/38

CPC classification number: G06F15/8061 ,  G06F9/30036 ,  G06F9/3814 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3877 ,  G06F13/16 ,  G06F13/4059

Abstract: Methods and apparatuses relating to tightly-coupled heterogeneous computing are described. In one embodiment, a hardware processor includes a plurality of execution units in parallel, a switch to connect inputs of the plurality of execution units to outputs of a first buffer and a plurality of memory banks and connect inputs of the plurality of memory banks and a plurality of second buffers in parallel to outputs of the first buffer, the plurality of memory banks, and the plurality of execution units, and an offload engine with inputs connected to outputs of the plurality of second buffers.