公开(公告)号：US09612986B2

公开(公告)日：2017-04-04

申请号：US14538871

申请日：2014-11-12

Applicant: INTEL CORPORATION

Inventor： Venkatraman Iyer ,  Darren S. Jue ,  Sitaraman Iyer

IPC: G06F13/42 ,  G06F13/40 ,  G06N99/00

CPC classification number: G06F13/4004 ,  G06F13/4221 ,  G06N99/005 ,  Y02D10/14 ,  Y02D10/151

Abstract: A set of training sequences is generated, each training sequence to include a respective training sequence header, and the training sequence header is to be DC-balanced over the set of training sequences. The set of training sequences can be combined with electric ordered sets to form supersequences for use in such tasks as link adaptation, link state transitions, byte lock, deskew, and other tasks.

公开(公告)号：US10795841B2

公开(公告)日：2020-10-06

申请号：US16284742

申请日：2019-02-25

Applicant: Intel Corporation

Inventor： Venkatraman Iyer ,  Darren Jue ,  Sitaraman Iyer

IPC: G06F13/40 ,  G06N20/00 ,  G06F13/42

Abstract: A supersequence is generated that includes a sequence including an electrical ordered set (EOS) and a plurality of training sequences. The plurality of training sequences include a predefined number of training sequences corresponding to a respective one of a plurality of training states with which the supersequence is to be associated, each training sequence in the plurality of training sequences is to include a respective training sequence header and a training sequence payload, the training sequence payloads of the plurality of training sequences are to be sent scrambled and the training sequence headers of the plurality of training sequences are to be sent unscrambled.

公开(公告)号：US20190391945A1

公开(公告)日：2019-12-26

申请号：US16284742

申请日：2019-02-25

Applicant: Intel Corporation

Inventor： Venkatraman Iyer ,  Darren Jue ,  Sitaraman Iyer

IPC: G06F13/40 ,  G06F13/42 ,  G06N20/00

Abstract: A supersequence is generated that includes a sequence including an electrical ordered set (EOS) and a plurality of training sequences. The plurality of training sequences include a predefined number of training sequences corresponding to a respective one of a plurality of training states with which the supersequence is to be associated, each training sequence in the plurality of training sequences is to include a respective training sequence header and a training sequence payload, the training sequence payloads of the plurality of training sequences are to be sent scrambled and the training sequence headers of the plurality of training sequences are to be sent unscrambled.

公开(公告)号：US09965370B2

公开(公告)日：2018-05-08

申请号：US14757882

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Venkatraman Iyer ,  Zuoguo Wu ,  Jeffrey Ou ,  Sitaraman Iyer

IPC: G06F13/00 ,  G06F11/30 ,  G06F13/42 ,  G06F1/26

CPC classification number: G06F11/3051 ,  G06F1/263 ,  G06F13/4282

Abstract: A port of a first device includes remote device detection logic to detect, on a link, a remote second device, determine, from a voltage generated at the port, whether the second device is direct current (DC)-coupled or alternating current (AC)-coupled to the link, and select one of first settings or second settings to be applied at the port in communications over the link with the second device based on whether the second device is DC-coupled or AC-coupled.

公开(公告)号：US20170185502A1

公开(公告)日：2017-06-29

申请号：US14757882

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Venkatraman Iyer ,  Zuoguo Wu ,  Jeffrey Ou ,  Sitaraman Iyer

IPC: G06F11/30 ,  G06F1/26 ,  G06F13/42

CPC classification number: G06F11/3051 ,  G06F1/263 ,  G06F13/4282

Abstract: A port of a first device includes remote device detection logic to detect, on a link, a remote second device, determine, from a voltage generated at the port, whether the second device is direct current (DC)-coupled or alternating current (AC)-coupled to the link, and select one of first settings or second settings to be applied at the port in communications over the link with the second device based on whether the second device is DC-coupled or AC-coupled.