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公开(公告)号:US10158578B2
公开(公告)日:2018-12-18
申请号:US15269295
申请日:2016-09-19
Applicant: INTEL CORPORATION
Inventor: Cristian Florin Dumitrescu , Andrey Chilikin , Pierre Laurent , Kannan Babu Ramia , Sravanthi Tangeda
IPC: H04L12/14 , H04L12/869 , H04L12/873 , H04L12/815 , H04L12/863 , H04L12/819 , H04L12/801 , H04L12/813 , H04L12/865 , H04L12/803 , H04L12/851
Abstract: One embodiment provides a network device. The network device includes a a processor including at least one processor core; a network interface configured to transmit and receive packets at a line rate; a memory configured to store a scheduler hierarchical data structure; and a scheduler module. The scheduler module is configured to prefetch a next active pipe structure, the next active pipe structure included in the hierarchical data structure, update credits for a current pipe and an associated subport, identify a next active traffic class within the current pipe based, at least in part, on a current pipe data structure, select a next queue associated with the identified next active traffic class, and schedule a next packet from the selected next queue for transmission by the network interface if available traffic shaping token bucket credits and available traffic class credits are greater than or equal to a next packet credits.
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公开(公告)号:US11494212B2
公开(公告)日:2022-11-08
申请号:US16144388
申请日:2018-09-27
Applicant: Intel Corporation
Inventor: Ranganath Sunku , Dinesh Kumar , Irene Liew , Kavindya Deegala , Sravanthi Tangeda
IPC: G06F9/455 , G06F9/50 , H04L12/931 , G06F15/16 , H04L15/16 , H04L49/00 , H04L41/0823 , H04L12/70
Abstract: Technologies for adaptive platform resource management include a compute node to manage a processor core mapping scheme between virtual machines (VMs) and a virtual switch of the compute node via a set of virtual ports. The virtual switch is also coupled to a network interface controller (NIC) of the compute node via another set of virtual ports. Each of the VMs is configured to either provide ingress or egress to the NIC or provide ingress/egress across the VMs, via the virtual ports. The virtual ports for providing ingress or egress to the NIC are pinned to a same processor core of a processor of the compute node, and each of the virtual ports for providing ingress and/or egress across the VMs are pinned to a respective processor core of the processor such that data is transferred across VMs by coupled virtual ports that are pinned to the same processor core.
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公开(公告)号:US20190042298A1
公开(公告)日:2019-02-07
申请号:US16144388
申请日:2018-09-27
Applicant: Intel Corporation
Inventor: Ranganath Sunku , Dinesh Kumar , Irene Liew , Kavindya Deegala , Sravanthi Tangeda
IPC: G06F9/455 , G06F9/50 , H04L12/931
Abstract: Technologies for adaptive platform resource management include a compute node to manage a processor core mapping scheme between virtual machines (VMs) and a virtual switch of the compute node via a set of virtual ports. The virtual switch is also coupled to a network interface controller (NIC) of the compute node via another set of virtual ports. Each of the VMs is configured to either provide ingress or egress to the NIC or provide ingress/egress across the VMs, via the virtual ports. The virtual ports for providing ingress or egress to the NIC are pinned to a same processor core of a processor of the compute node, and each of the virtual ports for providing ingress and/or egress across the VMs are pinned to a respective processor core of the processor such that data is transferred across VMs by coupled virtual ports that are pinned to the same processor core.
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公开(公告)号:US20170149678A1
公开(公告)日:2017-05-25
申请号:US15396488
申请日:2016-12-31
Applicant: INTEL CORPORATION
Inventor: Cristian Florin Dumitrescu , Andrey Chilikin , Pierre Laurent , Kannan Babu Ramia , Sravanthi Tangeda
IPC: H04L12/869 , H04L12/803 , H04L12/819 , H04L12/813 , H04L12/815 , H04L12/851
CPC classification number: H04L47/60 , H04L12/1439 , H04L47/10 , H04L47/125 , H04L47/20 , H04L47/21 , H04L47/215 , H04L47/22 , H04L47/2408 , H04L47/2433 , H04L47/2441 , H04L47/39 , H04L47/50 , H04L47/527 , H04L47/623 , H04L47/6255 , H04L47/627 , H04L47/6275
Abstract: One embodiment provides a network device. The network device includes a a processor including at least one processor core; a network interface configured to transmit and receive packets at a line rate; a memory configured to store a scheduler hierarchical data structure; and a scheduler module. The scheduler module is configured to prefetch a next active pipe structure, the next active pipe structure included in the hierarchical data structure, update credits for a current pipe and an associated subport, identify a next active traffic class within the current pipe based, at least in part, on a current pipe data structure, select a next queue associated with the identified next active traffic class, and schedule a next packet from the selected next queue for transmission by the network interface if available traffic shaping token bucket credits and available traffic class credits are greater than or equal to a next packet credits.
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公开(公告)号:US10091122B2
公开(公告)日:2018-10-02
申请号:US15396488
申请日:2016-12-31
Applicant: INTEL CORPORATION
Inventor: Cristian Florin Dumitrescu , Andrey Chilikin , Pierre Laurent , Kannan Babu Ramia , Sravanthi Tangeda
IPC: H04L12/869 , H04L12/815 , H04L12/851 , H04L12/819 , H04L12/813 , H04L12/803
Abstract: One embodiment provides a network device. The network device includes a a processor including at least one processor core; a network interface configured to transmit and receive packets at a line rate; a memory configured to store a scheduler hierarchical data structure; and a scheduler module. The scheduler module is configured to prefetch a next active pipe structure, the next active pipe structure included in the hierarchical data structure, update credits for a current pipe and an associated subport, identify a next active traffic class within the current pipe based, at least in part, on a current pipe data structure, select a next queue associated with the identified next active traffic class, and schedule a next packet from the selected next queue for transmission by the network interface if available traffic shaping token bucket credits and available traffic class credits are greater than or equal to a next packet credits.
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公开(公告)号:US20170070356A1
公开(公告)日:2017-03-09
申请号:US15269295
申请日:2016-09-19
Applicant: INTEL CORPORATION
Inventor: Cristian Florin Dumitrescu , Andrey Chilikin , Pierre Laurent , Kannan Babu Ramia , Sravanthi Tangeda
IPC: H04L12/14 , H04L12/801 , H04L12/863 , H04L12/865 , H04L12/819 , H04L12/815
CPC classification number: H04L47/60 , H04L12/1439 , H04L47/10 , H04L47/125 , H04L47/20 , H04L47/21 , H04L47/215 , H04L47/22 , H04L47/2408 , H04L47/2433 , H04L47/2441 , H04L47/39 , H04L47/50 , H04L47/527 , H04L47/623 , H04L47/6255 , H04L47/627 , H04L47/6275
Abstract: One embodiment provides a network device. The network device includes a a processor including at least one processor core; a network interface configured to transmit and receive packets at a line rate; a memory configured to store a scheduler hierarchical data structure; and a scheduler module. The scheduler module is configured to prefetch a next active pipe structure, the next active pipe structure included in the hierarchical data structure, update credits for a current pipe and an associated subport, identify a next active traffic class within the current pipe based, at least in part, on a current pipe data structure, select a next queue associated with the identified next active traffic class, and schedule a next packet from the selected next queue for transmission by the network interface if available traffic shaping token bucket credits and available traffic class credits are greater than or equal to a next packet credits.
Abstract translation: 一个实施例提供一种网络设备。 网络设备包括:处理器,包括至少一个处理器核心; 网络接口,被配置为以线路速率发送和接收分组; 存储器,被配置为存储调度器分层数据结构; 和调度器模块。 调度器模块被配置为预取下一个活动管道结构,包括在分级数据结构中的下一个主动管道结构,更新当前管道和相关联的子端口的信用,至少基于当前管道识别下一个活动业务类别 部分地,在当前的管道数据结构上,选择与所识别的下一个活动业务类别相关联的下一个队列,并且如果可用的流量整形令牌桶信用和可用业务类别,则可以从所选择的下一个队列调度下一个分组以供网络接口传输 信用额度大于或等于下一个信用额度。
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