公开(公告)号：US10990146B2

公开(公告)日：2021-04-27

申请号：US16359810

申请日：2019-03-20

Applicant: Intel Corporation

Inventor： Ramnarayanan Muthukaruppan ,  Pradipta Patra ,  Gaurav Goel ,  Uday Bhaskar Kadali

IPC: G06F1/00 ,  G06F1/26 ,  G05F1/59

Abstract: Described is a voltage regulator with adaptive gain, which comprises: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a load, and to receive a second power supply as input; an analog-to-digital converter (ADC) to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative of the first power supply and to generate the digital bus for controlling the plurality of power-gate transistors such that a transfer function of the plurality of power-gate transistors is substantially linear over an operating range.

公开(公告)号：US09766678B2

公开(公告)日：2017-09-19

申请号：US13758897

申请日：2013-02-04

Applicant: Intel Corporation

Inventor： Ramnarayanan Muthukaruppan ,  Harish K. Krishnamurthy ,  Mohit Verma ,  Pradipta Patra ,  Uday Bhaskar Kadali

IPC: G06F9/00 ,  G06F1/32

CPC classification number: G06F1/32 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  Y02D10/152 ,  Y02D10/172

Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.

公开(公告)号：US10185382B2

公开(公告)日：2019-01-22

申请号：US15292067

申请日：2016-10-12

Applicant: Intel Corporation

Inventor： Ramnarayanan Muthukaruppan ,  Harish K. Krishnamurthy ,  Mohit Verma ,  Pradipta Patra ,  Uday Bhaskar Kadali

IPC: G06F1/00 ,  G06F1/32

Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.

公开(公告)号：US10345881B2

公开(公告)日：2019-07-09

申请号：US15653764

申请日：2017-07-19

Applicant: Intel Corporation

Inventor： Ramnarayanan Muthukaruppan ,  Harish K. Krishnamurthy ,  Mohit Verma ,  Pradipta Patra ,  Uday Bhaskar Kadali

IPC: G06F9/00 ,  G06F1/32 ,  G06F1/3234 ,  G06F1/3296 ,  G06F1/324

Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.

公开(公告)号：US10268249B2

公开(公告)日：2019-04-23

申请号：US15025871

申请日：2013-12-18

Applicant: Intel Corporation

Inventor： Ramnarayanan Muthukaruppan ,  Pradipta Patra ,  Gaurav Goel ,  Uday Bhaskar Kadali

IPC: G06F1/26 ,  G05F1/59

Abstract: Described is a voltage regulator with adaptive gain, which comprises: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a load, and to receive a second power supply as input; an analog-to-digital converter (ADC) to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative of the first power supply and to generate the digital bus for controlling the plurality of power-gate transistors such that a transfer function of the plurality of power-gate transistors is substantially linear over an operating range.

公开(公告)号：US20140344589A1

公开(公告)日：2014-11-20

申请号：US14129593

申请日：2012-12-21

Applicant: INTEL CORPORATION

Inventor： Ramnarayanan Muthukaruppan ,  Pradyumna Agashe ,  Uday Bhaskar Kadali ,  Jnaneshwar Madugonda

IPC: G05F1/575 ,  G06F1/26

CPC classification number: G05F1/575 ,  G06F1/26 ,  H02M3/07 ,  H02M2003/077

Abstract: Methods and systems to regulate a voltage with multiple selectable voltage regulator (VR) modes, using multiple corresponding circuits and/or a configurable circuit. The circuit may be configurable for one or more of a power-gate VR mode, a switched-capacitor VR (SCVR) mode, and a linear mode, such as a low drop-out (LDO) VR mode. A feedback controller, such as a proportional-integral-derivative (PID) controller, may configure and/or control a multi-mode VR for a selected VR mode. The feedback controller may select a VR mode based on a reference voltage and voltage ranges associated with the VR modes. The circuit may be configurable as banks of VRs, and the controller may be implemented to transition between VR modes by switching sub-banks between modes until the transition is complete.

Abstract translation: 使用多个可选择的电压调节器（VR）模式来调节电压的方法和系统，使用多个相应的电路和/或可配置电路。 电路可以配置为电源门VR模式，开关电容器VR（SCVR）模式和线性模式（例如低压差（LDO）VR模式）中的一个或多个。 诸如比例积分微分（PID）控制器的反馈控制器可以配置和/或控制用于所选VR模式的多模式VR。 反馈控制器可以基于与VR模式相关联的参考电压和电压范围来选择VR模式。 该电路可以被配置为VR组，并且可以通过在模式之间切换子组来实现控制器以在VR模式之间转换，直到转换完成。