公开(公告)号：US20160188334A1

公开(公告)日：2016-06-30

申请号：US14582784

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Victor Lee ,  Ugonna Echeruo ,  George Chrysos ,  Naveen Mellempudi

IPC: G06F9/30

CPC classification number: G06F9/30036

Abstract: Methods and apparatuses relating to a vector instruction with a register operand with an elemental offset are described. In one embodiment, a hardware processor includes a decode unit to decode a vector instruction with a register operand with an elemental offset to access a first number of elements in a register specified by the register operand, wherein the first number is a total number of elements in the register minus the elemental offset, access a second number of elements in a next logical register, wherein the second number is the elemental offset, and combine the first number of elements and the second number of elements as a data vector, and an execution unit to execute the vector instruction on the data vector.

Abstract translation: 描述与具有具有基本偏移的寄存器操作数的向量指令相关的方法和装置。 在一个实施例中，硬件处理器包括解码单元，用于对具有基本偏移量的寄存器操作数解码向量指令，以访问由寄存器操作数指定的寄存器中的第一数量的元素，其中第一个数字是元素的总数 在所述寄存器中减去所述元素偏移量，访问下一逻辑寄存器中的第二数量的元素，其中所述第二数量是所述元素偏移量，并且将所述第一数量的元素和所述第二数量的元素组合为数据向量，以及执行 单元来执行数据向量的向量指令。

公开(公告)号：US11256626B2

公开(公告)日：2022-02-22

申请号：US16837833

申请日：2020-04-01

Applicant: Intel Corporation

Inventor： Wim Heirman ,  Ibrahim Hur ,  Ugonna Echeruo ,  Stijn Eyerman ,  Kristof Du Bois

IPC: G06F12/08 ,  G06F12/0862

Abstract: Apparatus, method, and system for enhancing data prefetching based on non-uniform memory access (NUMA) characteristics are described herein. An apparatus embodiment includes a system memory, a cache, and a prefetcher. The system memory includes multiple memory regions, at least some of which are associated with different NUMA characteristic (access latency, bandwidth, etc.) than others. Each region is associated with its own set of prefetch parameters that are set in accordance to their respective NUMA characteristics. The prefetcher monitors data accesses to the cache and generates one or more prefetch requests to fetch data from the system memory to the cache based on the monitored data accesses and the set of prefetch parameters associated with the memory region from which data is to be fetched. The set of prefetcher parameters may include prefetch distance, training-to-stable threshold, and throttle threshold.

公开(公告)号：US10719317B2

公开(公告)日：2020-07-21

申请号：US16003555

申请日：2018-06-08

Applicant: INTEL CORPORATION

Inventor： Victor Lee ,  Ugonna Echeruo ,  George Chrysos ,  Naveen Mellempudi

IPC: G06F9/30

Abstract: Methods and apparatuses relating to a vector instruction with a register operand with an elemental offset are described. In one embodiment, a hardware processor includes a decode unit to decode a vector instruction with a register operand with an elemental offset to access a first number of elements in a register specified by the register operand, wherein the first number is a total number of elements in the register minus the elemental offset, access a second number of elements in a next logical register, wherein the second number is the elemental offset, and combine the first number of elements and the second number of elements as a data vector, and an execution unit to execute the vector instruction on the data vector.

公开(公告)号：US20190138305A1

公开(公告)日：2019-05-09

申请号：US16003555

申请日：2018-06-08

Applicant: INTEL CORPORATION

Inventor： Victor Lee ,  Ugonna Echeruo ,  George Chrysos ,  Naveen Mellempudi

IPC: G06F9/30

CPC classification number: G06F9/30036

Abstract: Methods and apparatuses relating to a vector instruction with a register operand with an elemental offset are described. In one embodiment, a hardware processor includes a decode unit to decode a vector instruction with a register operand with an elemental offset to access a first number of elements in a register specified by the register operand, wherein the first number is a total number of elements in the register minus the elemental offset, access a second number of elements in a next logical register, wherein the second number is the elemental offset, and combine the first number of elements and the second number of elements as a data vector, and an execution unit to execute the vector instruction on the data vector.

公开(公告)号：US20230091205A1

公开(公告)日：2023-03-23

申请号：US17479582

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Adrian Moga ,  Ugonna Echeruo ,  Eduard Roytman ,  Krishnakanth Sistla ,  Joseph Nuzman ,  Brinda Ganesh ,  Meenakshisundaram Chinthamani ,  Yen-Cheng Liu ,  Sai Prashanth Muralidhara ,  Vivek Kozhikkottu ,  Hanna Alam ,  Narasimha Sridhar Srirangam

IPC: G06F12/0862 ,  G06F13/28

Abstract: Methods and apparatus relating to memory side prefetch architecture for improved memory bandwidth are described. In an embodiment, logic circuitry transmits a Direct Memory Controller Prefetch (DMCP) request to cause a prefetch of data from memory. A memory controller receives the DMCP request and issues a plurality of read operations to the memory in response to the DMCP request. Data read from the memory is stored in a storage structure in response to the plurality of read operations. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200233806A1

公开(公告)日：2020-07-23

申请号：US16837833

申请日：2020-04-01

Applicant: Intel Corporation

Inventor： Wim Heirman ,  Ibrahim Hur ,  Ugonna Echeruo ,  Stijn Eyerman ,  Kristof Du Bois

IPC: G06F12/0862

Abstract: Apparatus, method, and system for enhancing data prefetching based on non-uniform memory access (NUMA) characteristics are described herein. An apparatus embodiment includes a system memory, a cache, and a prefetcher. The system memory includes multiple memory regions, at least some of which are associated with different NUMA characteristic (access latency, bandwidth, etc.) than others. Each region is associated with its own set of prefetch parameters that are set in accordance to their respective NUMA characteristics. The prefetcher monitors data accesses to the cache and generates one or more prefetch requests to fetch data from the system memory to the cache based on the monitored data accesses and the set of prefetch parameters associated with the memory region from which data is to be fetched. The set of prefetcher parameters may include prefetch distance, training-to-stable threshold, and throttle threshold.

公开(公告)号：US20200004684A1

公开(公告)日：2020-01-02

申请号：US16024527

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Wim Heirman ,  Ibrahim Hur ,  Ugonna Echeruo ,  Stijn Eyerman ,  Kristof Du Bois

IPC: G06F12/0862

Abstract: Apparatus, method, and system for enhancing data prefetching based on non-uniform memory access (NUMA) characteristics are described herein. An apparatus embodiment includes a system memory, a cache, and a prefetcher. The system memory includes multiple memory regions, at least some of which are associated with different NUMA characteristic (access latency, bandwidth, etc.) than others. Each region is associated with its own set of prefetch parameters that are set in accordance to their respective NUMA characteristics. The prefetcher monitors data accesses to the cache and generates one or more prefetch requests to fetch data from the system memory to the cache based on the monitored data accesses and the set of prefetch parameters associated with the memory region from which data is to be fetched. The set of prefetcher parameters may include prefetch distance, training-to-stable threshold, and throttle threshold.

公开(公告)号：US09996347B2

公开(公告)日：2018-06-12

申请号：US14582784

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Victor Lee ,  Ugonna Echeruo ,  George Chrysos ,  Naveen Mellempudi

IPC: G06F9/30

CPC classification number: G06F9/30036

Abstract: Methods and apparatuses relating to a vector instruction with a register operand with an elemental offset are described. In one embodiment, a hardware processor includes a decode unit to decode a vector instruction with a register operand with an elemental offset to access a first number of elements in a register specified by the register operand, wherein the first number is a total number of elements in the register minus the elemental offset, access a second number of elements in a next logical register, wherein the second number is the elemental offset, and combine the first number of elements and the second number of elements as a data vector, and an execution unit to execute the vector instruction on the data vector.