公开(公告)号：US10649899B2

公开(公告)日：2020-05-12

申请号：US15505879

申请日：2014-09-25

Applicant: INTEL CORPORATION

Inventor： Sai Luo ,  Tin-Fook Ngai ,  Hu Chen ,  Xiaocheng Zhou ,  Chunxiao Lin ,  Kang Zhao

IPC: G06F12/00 ,  G06F12/0842 ,  G06F11/36 ,  G06F12/0831 ,  G06F12/0875

Abstract: A processing device includes a processing core, coupled to a memory, to execute a task including a code segment identified as being monitored and a kernel recorder, coupled to the processing core via a core interface. The kernel recorder includes a first filter circuit to responsive to determining that the task being executed enters the code segment, set the kernel recorder to a first mode under which the kernel recorder is to record, in a first record, a plurality of memory addresses accessed by the code segment, and responsive to determining that the execution of the task exits the code segment, set the kernel recorder to a second mode under which the kernel recorder is to detect a write operation to a memory address recorded in the first record and record the memory address in a second record.

公开(公告)号：US09400702B2

公开(公告)日：2016-07-26

申请号：US14320985

申请日：2014-07-01

Applicant: Intel Corporation

Inventor： Hu Chen ,  Ying Gao ,  Xiaocheng Zhou ,  Shoumeng Yan ,  Peinan Zhang ,  Mohan Rajagopalan ,  Jesse Fang ,  Avi Mendelson ,  Bratin Saha

IPC: G06F9/54 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06F9/544 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/1009 ,  G06F12/1063 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/109 ,  G06F2212/161 ,  G06F2212/622 ,  G06F2212/656 ,  G06F2212/657 ,  G06F2212/682 ,  G06T1/20 ,  G06T1/60

Abstract: Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.

公开(公告)号：US20150113255A1

公开(公告)日：2015-04-23

申请号：US14569454

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Shoumeng Yan ,  Xiaocheng Zhou ,  Hu Chen ,  Ying Gao ,  Sai Luo ,  Bratin Saha

IPC: G06F12/10 ,  G06F9/38

CPC classification number: G06F12/1072 ,  G06F8/447 ,  G06F9/3863 ,  G06F9/3885 ,  G06F9/548 ,  G06F2212/657

Abstract: A computing platform may include heterogeneous processors (e.g., CPU and a GPU) to support sharing of virtual functions between such processors. In one embodiment, a CPU side vtable pointer used to access a shared object from the CPU 110 may be used to determine a GPU vtable if a GPU-side table exists. In another embodiment, a shared non-coherent region, which may not maintain data consistency, may be created within the shared virtual memory. The CPU and the GPU side data stored within the shared non-coherent region may have a same address as seen from the CPU and the GPU side. However, the contents of the CPU-side data may be different from that of GPU-side data as shared virtual memory may not maintain coherency during the run-time. In one embodiment, the vptr may be modified to point to the CPU vtable and GPU vtable stored in the shared virtual memory.

Abstract translation: 计算平台可以包括异构处理器（例如，CPU和GPU），以支持这些处理器之间的虚拟功能的共享。 在一个实施例中，如果GPU侧表存在，则用于从CPU 110访问共享对象的CPU侧vtable指针可用于确定GPU vtable。 在另一个实施例中，可以在共享虚拟存储器内创建可能不维持数据一致性的共享非相干区域。 存储在共享非相干区域内的CP​​U和GPU侧数据可以具有与CPU和GPU侧所见相同的地址。 然而，CPU侧数据的内容可能与GPU侧数据的内容不同，因为共享虚拟存储器可能在运行期间不能维持一致性。 在一个实施例中，可以修改vptr以指向存储在共享虚拟存储器中的CPU vtable和GPU vtable。

公开(公告)号：US09236054B2

公开(公告)日：2016-01-12

申请号：US14006840

申请日：2012-09-29

Applicant: INTEL CORPORATION

Inventor： Xiaocheng Zhou ,  Shoumeng Yan

IPC: G10L19/00 ,  G10L19/16

CPC classification number: G10L19/0019 ,  G10L19/167

Abstract: An audio accelerator includes a decoder to decode first and second sets of data blocks, a processor to process the first and second sets of decoded data blocks, a storage area to store the first and second sets of processed data blocks, and a controller to generate interrupt signals for controlling operation of the decoder. The controller may control a rate at which data blocks are to be decoded by the decoder to reduce a time gap between outputting adjacent ones of the data blocks from the first and second sets in the storage area.

Abstract translation: 音频加速器包括：解码器，用于对第一和第二组数据块进行解码;处理器，用于处理第一和第二组解码的数据块;存储区域，用于存储第一和第二组经处理的数据块;以及控制器， 用于控制解码器操作的中断信号。 控制器可以控制解码器解码数据块的速率，以减少从存储区域中的第一组和第二组输出相邻数据块之间的时间间隔。

公开(公告)号：US08997114B2

公开(公告)日：2015-03-31

申请号：US14173071

申请日：2014-02-05

Applicant: Intel Corporation

Inventor： Xiaocheng Zhou ,  Shoumeng Yan ,  Ying Gao ,  Hu Chen ,  Peinan Zhang ,  Mohan Rajagopalan ,  Avi Mendelson ,  Bratin Saha

IPC: G06F9/44 ,  G06F13/14 ,  G06F13/00 ,  G06T1/60 ,  G06F9/54 ,  G06F12/10

CPC classification number: G06F9/544 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/1009 ,  G06F12/1063 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/109 ,  G06F2212/161 ,  G06F2212/622 ,  G06F2212/656 ,  G06F2212/657 ,  G06F2212/682 ,  G06T1/20 ,  G06T1/60

Abstract: Embodiments of the invention provide language support for CPU-GPU platforms. In one embodiment, code can be flexibly executed on both the CPU and GPU. CPU code can offload a kernel to the GPU. That kernel may in turn call preexisting libraries on the CPU, or make other calls into CPU functions. This allows an application to be built without requiring the entire call chain to be recompiled. Additionally, in one embodiment data may be shared seamlessly between CPU and GPU. This includes sharing objects that may have virtual functions. Embodiments thus ensure the right virtual function gets invoked on the CPU or the GPU if a virtual function is called by either the CPU or GPU.

Abstract translation: 本发明的实施例为CPU-GPU平台提供语言支持。 在一个实施例中，可以在CPU和GPU两者上灵活地执行代码。 CPU代码可以将内核卸载到GPU。 该内核可能会调用CPU上的预先存在的库，或者调用其他CPU函数。 这允许构建应用程序，而不需要重新编译整个调用链。 此外，在一个实施例中，数据可以在CPU和GPU之间无缝共享。 这包括共享可能具有虚拟功能的对象。 因此，如果CPU或GPU调用虚拟功能，这些实施例可以确保在CPU或GPU上调用正确的虚拟功能。

公开(公告)号：US09710396B2

公开(公告)日：2017-07-18

申请号：US14503596

申请日：2014-10-01

Applicant: Intel Corporation

Inventor： Ying Gao ,  Hu Chen ,  Shoumeng Yan ,  Xiaocheng Zhou ,  Sai Luo ,  Bratin Saha

IPC: G06F12/02 ,  G06F12/109 ,  G06F9/46 ,  G06F9/54 ,  G06F15/167 ,  G06T1/20

CPC classification number: G06F12/109 ,  G06F9/466 ,  G06F9/544 ,  G06F15/167 ,  G06F2212/656 ,  G06F2212/657 ,  G06T1/20

Abstract: A computer system may comprise a computer platform and input-output devices. The computer platform may include a plurality of heterogeneous processors comprising a central processing unit (CPU) and a graphics processing unit (GPU) and a shared virtual memory supported by a physical private memory space of at least one heterogeneous processor or a physical shared memory shared by the heterogeneous processor. The CPU (producer) may create shared multi-version data and store such shared multi-version data in the physical private memory space or the physical shared memory. The GPU (consumer) may acquire or access the shared multi-version data.

公开(公告)号：US09588826B2

公开(公告)日：2017-03-07

申请号：US14566654

申请日：2014-12-10

Applicant: Intel Corporation

Inventor： Hu Chen ,  Ying Gao ,  Xiaocheng Zhou ,  Shoumeng Yan ,  Peinan Zhang ,  Mohan Rajagopalan ,  Jesse Fang ,  Avi Mendelson ,  Bratin Saha

IPC: G06F9/54 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06F9/544 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/1009 ,  G06F12/1063 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/109 ,  G06F2212/161 ,  G06F2212/622 ,  G06F2212/656 ,  G06F2212/657 ,  G06F2212/682 ,  G06T1/20 ,  G06T1/60

Abstract: Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.

Abstract translation: 本发明的实施例提供了一种用于CPU-GPU平台的编程模型。 特别地，本发明的实施例为集成和分立设备提供统一的编程模型。 该模型还适用于多个GPU卡和混合GPU系统（分立和集成）。 这允许软件供应商编写单个应用程序堆栈并将其定位到所有不同的平台。 另外，本发明的实施例提供了CPU和GPU之间的共享存储器模型。 而不是共享整个虚拟地址空间，只需要共享虚拟地址空间的一部分。 这允许在离散和集成设置中有效实现。

公开(公告)号：US20150123978A1

公开(公告)日：2015-05-07

申请号：US14566654

申请日：2014-12-10

Applicant: Intel Corporation

Inventor： Hu Chen ,  Ying Gao ,  Xiaocheng Zhou ,  Shoumeng Yan ,  Peinan Zhang ,  Mohan Rajagopalan ,  Jesse Fang ,  Avi Mendelson ,  Bratin Saha

IPC: G06F9/54 ,  G06T1/20 ,  G06F12/08 ,  G06T1/60

CPC classification number: G06F9/544 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/1009 ,  G06F12/1063 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/109 ,  G06F2212/161 ,  G06F2212/622 ,  G06F2212/656 ,  G06F2212/657 ,  G06F2212/682 ,  G06T1/20 ,  G06T1/60

Abstract: Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.

Abstract translation: 本发明的实施例提供了一种用于CPU-GPU平台的编程模型。 特别地，本发明的实施例为集成和分立设备提供统一的编程模型。 该模型还适用于多个GPU卡和混合GPU系统（分立和集成）。 这允许软件供应商编写单个应用程序堆栈并将其定位到所有不同的平台。 另外，本发明的实施例提供了CPU和GPU之间的共享存储器模型。 而不是共享整个虚拟地址空间，只需要共享虚拟地址空间的一部分。 这允许在离散和集成设置中有效实现。