公开(公告)号：US11815602B2

公开(公告)日：2023-11-14

申请号：US16644118

申请日：2017-10-03

Applicant: Intel Corporation

Inventor： Ganmei You ,  Zhigang Wang ,  Dawei Wang ,  Hu Chen

IPC: G01S17/89 ,  G06T7/521 ,  G01S17/931 ,  G01S7/4913 ,  G01S7/487 ,  G01S7/497

CPC classification number: G01S17/89 ,  G01S7/4873 ,  G01S7/4913 ,  G01S17/931 ,  G06T7/521 ,  G06T2207/20212

Abstract: A technology is described for mapping a physical environment. An example method may include receiving laser point data for laser light reflected from the physical environment and detected by a laser sensor. Points included in the laser point data can be correlated to grid cells in an environment map that represents the physical environment. Error ranges for the points correlated to the grid cells can be determined based in part on an error distribution. Occupation probabilities can then be calculated for the grid cells in the environment map using an interpolation technique and grid cell occupation probabilities for adjacent error grid cells selected based in part on the error ranges of the points, and the grid cells in the environment map can be updated with the occupation probabilities.

公开(公告)号：US20200271787A1

公开(公告)日：2020-08-27

申请号：US16644118

申请日：2017-10-03

Applicant: Intel Corporation

Inventor： Ganmei You ,  Zhigang Wang ,  Dawei Wang ,  Hu Chen

IPC: G01S17/89 ,  G01S17/931 ,  G01S7/487 ,  G01S7/4913

Abstract: A technology is described for mapping a physical environment. An example method may include receiving laser point data for laser light reflected from the physical environment and detected by a laser sensor. Points included in the laser point data can be correlated to grid cells in an environment map that represents the physical environment. Error ranges for the points correlated to the grid cells can be determined based in part on an error distribution. Occupation probabilities can then be calculated for the grid cells in the environment map using an interpolation technique and grid cell occupation probabilities for adjacent error grid cells selected based in part on the error ranges of the points, and the grid cells in the environment map can be updated with the occupation probabilities.

公开(公告)号：US09400702B2

公开(公告)日：2016-07-26

申请号：US14320985

申请日：2014-07-01

Applicant: Intel Corporation

Inventor： Hu Chen ,  Ying Gao ,  Xiaocheng Zhou ,  Shoumeng Yan ,  Peinan Zhang ,  Mohan Rajagopalan ,  Jesse Fang ,  Avi Mendelson ,  Bratin Saha

IPC: G06F9/54 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06F9/544 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/1009 ,  G06F12/1063 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/109 ,  G06F2212/161 ,  G06F2212/622 ,  G06F2212/656 ,  G06F2212/657 ,  G06F2212/682 ,  G06T1/20 ,  G06T1/60

Abstract: Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.

公开(公告)号：US20150113255A1

公开(公告)日：2015-04-23

申请号：US14569454

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Shoumeng Yan ,  Xiaocheng Zhou ,  Hu Chen ,  Ying Gao ,  Sai Luo ,  Bratin Saha

IPC: G06F12/10 ,  G06F9/38

CPC classification number: G06F12/1072 ,  G06F8/447 ,  G06F9/3863 ,  G06F9/3885 ,  G06F9/548 ,  G06F2212/657

Abstract: A computing platform may include heterogeneous processors (e.g., CPU and a GPU) to support sharing of virtual functions between such processors. In one embodiment, a CPU side vtable pointer used to access a shared object from the CPU 110 may be used to determine a GPU vtable if a GPU-side table exists. In another embodiment, a shared non-coherent region, which may not maintain data consistency, may be created within the shared virtual memory. The CPU and the GPU side data stored within the shared non-coherent region may have a same address as seen from the CPU and the GPU side. However, the contents of the CPU-side data may be different from that of GPU-side data as shared virtual memory may not maintain coherency during the run-time. In one embodiment, the vptr may be modified to point to the CPU vtable and GPU vtable stored in the shared virtual memory.

Abstract translation: 计算平台可以包括异构处理器（例如，CPU和GPU），以支持这些处理器之间的虚拟功能的共享。 在一个实施例中，如果GPU侧表存在，则用于从CPU 110访问共享对象的CPU侧vtable指针可用于确定GPU vtable。 在另一个实施例中，可以在共享虚拟存储器内创建可能不维持数据一致性的共享非相干区域。 存储在共享非相干区域内的CP​​U和GPU侧数据可以具有与CPU和GPU侧所见相同的地址。 然而，CPU侧数据的内容可能与GPU侧数据的内容不同，因为共享虚拟存储器可能在运行期间不能维持一致性。 在一个实施例中，可以修改vptr以指向存储在共享虚拟存储器中的CPU vtable和GPU vtable。

公开(公告)号：US08683487B2

公开(公告)日：2014-03-25

申请号：US13792427

申请日：2013-03-11

Applicant: Intel Corporation ,  Kerry Tweet

Inventor： Zhou Xiaocheng ,  Shoumeng Yan ,  Gao Ying ,  Hu Chen ,  Peinan Zhang ,  Mohan Rajagopalan ,  Avi Mendelson ,  Bratin Saha

IPC: G06F9/44 ,  G06F13/14 ,  G06F13/00

CPC classification number: G06F9/544 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/1009 ,  G06F12/1063 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/109 ,  G06F2212/161 ,  G06F2212/622 ,  G06F2212/656 ,  G06F2212/657 ,  G06F2212/682 ,  G06T1/20 ,  G06T1/60

Abstract: Embodiments of the invention provide language support for CPU-GPU platforms. In one embodiment, code can be flexibly executed on both the CPU and GPU. CPU code can offload a kernel to the GPU. That kernel may in turn call preexisting libraries on the CPU, or make other calls into CPU functions. This allows an application to be built without requiring the entire call chain to be recompiled. Additionally, in one embodiment data may be shared seamlessly between CPU and GPU. This includes sharing objects that may have virtual functions. Embodiments thus ensure the right virtual function gets invoked on the CPU or the GPU if a virtual function is called by either the CPU or GPU.

Abstract translation: 本发明的实施例为CPU-GPU平台提供语言支持。 在一个实施例中，可以在CPU和GPU两者上灵活地执行代码。 CPU代码可以将内核卸载到GPU。 该内核可能会调用CPU上的预先存在的库，或者调用其他CPU函数。 这允许构建应用程序，而不需要重新编译整个调用链。 此外，在一个实施例中，数据可以在CPU和GPU之间无缝共享。 这包括共享可能具有虚拟功能的对象。 因此，如果CPU或GPU调用虚拟功能，这些实施例可以确保在CPU或GPU上调用正确的虚拟功能。

公开(公告)号：US11675600B2

公开(公告)日：2023-06-13

申请号：US17054713

申请日：2018-12-18

Applicant: Intel Corporation

Inventor： Shuo Liu ,  Yipeng Yao ,  Hu Chen ,  Yifan Zhang ,  Jia Bao

IPC: G06F9/00 ,  G06F15/177 ,  G06F9/4401 ,  G07C5/08

CPC classification number: G06F9/4406 ,  G06F9/4403 ,  G07C5/0841

Abstract: Apparatuses, methods and storage medium associated with multi-phase/level boot technology, are disclosed herein. In embodiments, a method may include resuming an initial execution image of a computing platform from persistent storage to execute an initial task; and subsequently, resuming a full execution image of the computing platform from the persistent storage to execute one of a plurality of operational tasks. Other embodiments are also described and claimed.

公开(公告)号：US08997114B2

公开(公告)日：2015-03-31

申请号：US14173071

申请日：2014-02-05

Applicant: Intel Corporation

Inventor： Xiaocheng Zhou ,  Shoumeng Yan ,  Ying Gao ,  Hu Chen ,  Peinan Zhang ,  Mohan Rajagopalan ,  Avi Mendelson ,  Bratin Saha

IPC: G06F9/44 ,  G06F13/14 ,  G06F13/00 ,  G06T1/60 ,  G06F9/54 ,  G06F12/10

CPC classification number: G06F9/544 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/1009 ,  G06F12/1063 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/109 ,  G06F2212/161 ,  G06F2212/622 ,  G06F2212/656 ,  G06F2212/657 ,  G06F2212/682 ,  G06T1/20 ,  G06T1/60

Abstract: Embodiments of the invention provide language support for CPU-GPU platforms. In one embodiment, code can be flexibly executed on both the CPU and GPU. CPU code can offload a kernel to the GPU. That kernel may in turn call preexisting libraries on the CPU, or make other calls into CPU functions. This allows an application to be built without requiring the entire call chain to be recompiled. Additionally, in one embodiment data may be shared seamlessly between CPU and GPU. This includes sharing objects that may have virtual functions. Embodiments thus ensure the right virtual function gets invoked on the CPU or the GPU if a virtual function is called by either the CPU or GPU.

Abstract translation: 本发明的实施例为CPU-GPU平台提供语言支持。 在一个实施例中，可以在CPU和GPU两者上灵活地执行代码。 CPU代码可以将内核卸载到GPU。 该内核可能会调用CPU上的预先存在的库，或者调用其他CPU函数。 这允许构建应用程序，而不需要重新编译整个调用链。 此外，在一个实施例中，数据可以在CPU和GPU之间无缝共享。 这包括共享可能具有虚拟功能的对象。 因此，如果CPU或GPU调用虚拟功能，这些实施例可以确保在CPU或GPU上调用正确的虚拟功能。

公开(公告)号：US20230195201A1

公开(公告)日：2023-06-22

申请号：US18110603

申请日：2023-02-16

Applicant: Intel Corporation

Inventor： Junyuan Wang ,  Timothy Waite ,  Ziye Yang ,  Hu Chen ,  Zixuan Li ,  Anna Czarnowska ,  Olayinka Olubayo ,  Gordon McFadden

IPC: G06F1/324 ,  G06F9/50

CPC classification number: G06F1/324 ,  G06F9/5094

Abstract: An accelerator apparatus can include an interface to receive service requests from at least one processing core. The accelerator apparatus can include coprocessor circuitry coupled to the interface and comprised of multiple slices. The coprocessor circuitry can detect a performance type for the at least one processing core. The coprocessor circuitry can operate the plurality of coprocessor slices in at least one of a plurality of power modes based on the performance type detected for the at least one processing core. Some operations can be alternatively performed by an operating system on any processor coupled to the network.

公开(公告)号：US10649899B2

公开(公告)日：2020-05-12

申请号：US15505879

申请日：2014-09-25

Applicant: INTEL CORPORATION

Inventor： Sai Luo ,  Tin-Fook Ngai ,  Hu Chen ,  Xiaocheng Zhou ,  Chunxiao Lin ,  Kang Zhao

IPC: G06F12/00 ,  G06F12/0842 ,  G06F11/36 ,  G06F12/0831 ,  G06F12/0875

Abstract: A processing device includes a processing core, coupled to a memory, to execute a task including a code segment identified as being monitored and a kernel recorder, coupled to the processing core via a core interface. The kernel recorder includes a first filter circuit to responsive to determining that the task being executed enters the code segment, set the kernel recorder to a first mode under which the kernel recorder is to record, in a first record, a plurality of memory addresses accessed by the code segment, and responsive to determining that the execution of the task exits the code segment, set the kernel recorder to a second mode under which the kernel recorder is to detect a write operation to a memory address recorded in the first record and record the memory address in a second record.

公开(公告)号：US09552303B2

公开(公告)日：2017-01-24

申请号：US15218799

申请日：2016-07-25

Applicant: Intel Corporation

Inventor： Ravindra Babu Ganapathi ,  Hu Chen

IPC: G06F3/06 ,  G06F12/08 ,  G06F12/0817 ,  G06F12/1009 ,  G06F12/128 ,  G06F13/16 ,  G06F12/10 ,  G06F12/12

CPC classification number: G06F12/1009 ,  G06F3/0614 ,  G06F3/0655 ,  G06F3/0671 ,  G06F12/08 ,  G06F12/0822 ,  G06F12/128 ,  G06F13/1663 ,  G06F2212/50 ,  G06F2212/6026 ,  G06F2212/621 ,  G06F2212/65 ,  G06F2212/657

Abstract: A method and system for maintaining release consistency in shared memory programming on a computing device having multiple processing units includes, in response to a page fault, initiating a transfer, from one processing unit to another, of data associated with more than one but less than all of the pages of shared memory.

Abstract translation: 一种用于在具有多个处理单元的计算设备上维持共享存储器编程中的释放一致性的方法和系统包括响应于页面故障，从一个处理单元发起与多个处理单元相关联的数据的传输 共享内存的所有页面。