公开(公告)号：US10289431B2

公开(公告)日：2019-05-14

申请号：US15283318

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Xueyan Wang ,  Wenjuan Mao ,  Qiang Li ,  John V. Lovelace ,  James R. Goffena

IPC: G06F9/445 ,  G06F13/00 ,  G06F12/0875

Abstract: Technologies for control and status register (CSR) access include a computing device that starts a firmware initialization phase. The firmware accesses a CSR at an abstract CSR address. The computing device determines whether an upper part of the CSR address matches a cached upper part of a previously accessed CSR address. If the upper parts do not match, the computing device converts the CSR address into a physical address and caches the upper part of the CSR address and the upper part of the physical address. If the upper parts match, the computing device combines a cached upper part of a previously accessed physical address with an offset of the CSR address. The upper part may include 20 bits and the lower part may include 12 bits. The physical address may be a PCIe address of the CSR added with an MMCFG base address. Other embodiments are described and claimed.

公开(公告)号：US20230305927A1

公开(公告)日：2023-09-28

申请号：US18326918

申请日：2023-05-31

Applicant: Intel Corporation

Inventor： Xueyan Wang ,  Vincent J. Zimmer ,  Qing Yang Li

IPC: G06F11/14 ,  G06F11/07

CPC classification number: G06F11/1417 ,  G06F11/0721

Abstract: Register operations to cause a processor unit to enter into a management operating mode are stored in a dedicated buffer in the processor unit and are executed by the processor unit when the processor unit is to enter into a management operating mode. The register operations can be stored in the buffer during computing system startup or by out-of-band provisioning during computing system runtime. The register operations can save a state of the processor unit as part of entering the management operating mode and restore the state when the processor unit exits the management operation mode. In computing systems comprising multiple processor units, the register operations can cause one of the processor units to execute management operating mode instructions and one or more other processor units to enter into an idle mode while the processor units are in the management operating mode.

公开(公告)号：US20180095889A1

公开(公告)日：2018-04-05

申请号：US15283318

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Xueyan Wang ,  Wenjuan Mao ,  Qiang Li ,  John V. Lovelace ,  James R. Goffena

IPC: G06F12/0895 ,  G06F12/0875 ,  G06F12/10 ,  G06F9/445

CPC classification number: G06F9/44505 ,  G06F12/0875 ,  G06F13/00 ,  G06F2212/452

Abstract: Technologies for control and status register (CSR) access include a computing device that starts a firmware initialization phase. The firmware accesses a CSR at an abstract CSR address. The computing device determines whether an upper part of the CSR address matches a cached upper part of a previously accessed CSR address. If the upper parts do not match, the computing device converts the CSR address into a physical address and caches the upper part of the CSR address and the upper part of the physical address. If the upper parts match, the computing device combines a cached upper part of a previously accessed physical address with an offset of the CSR address. The upper part may include 20 bits and the lower part may include 12 bits. The physical address may be a PCIe address of the CSR added with an MMCFG base address. Other embodiments are described and claimed.

公开(公告)号：US11782645B2

公开(公告)日：2023-10-10

申请号：US17568956

申请日：2022-01-05

Applicant: INTEL CORPORATION

Inventor： Zhi Yong Chen ,  Zhiqiang Qin ,  Xueyan Wang ,  Fang Yuan

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0673

Abstract: Logic may store data structures for two or more processors in memory such as cache, system management memory, protected memory, or other memory. Logic may compress the data structures to be stored in the memory. Logic may determine a reference data structure, store the reference data structure in the memory, determine a difference between a data structure for a second processor and the reference data structure, and store the difference in the memory. Logic may store the difference in the memory within a data structure such as a linked list or a bitmap. Logic may decompress the difference by combining the difference with the reference data structure. Logic may expand the useable data region to include cache in the two or more processors. Logic may instruct two or more processors to store their processor data structures in their respective caches and perform initialization with the processor data structures.

公开(公告)号：US11288010B2

公开(公告)日：2022-03-29

申请号：US16638694

申请日：2017-09-25

Applicant: INTEL CORPORATION

Inventor： Zhi Yong Chen ,  Zhiqiang Qin ,  Xueyan Wang ,  Fang Yuan

IPC: G06F3/06

Abstract: Logic may store data structures for two or more processors in memory such as cache, system management memory, protected memory, or other memory. Logic may compress the data structures to be stored in the memory. Logic may determine a reference data structure, store the reference data structure in the memory, determine a difference between a data structure for a second processor and the reference data structure, and store the difference in the memory. Logic may store the difference in the memory within a data structure such as a linked list or a bitmap. Logic may decompress the difference by combining the difference with the reference data structure. Logic may expand the useable data region to include cache in the two or more processors. Logic may instruct two or more processors to store their processor data structures in their respective caches and perform initialization with the processor data structures.