METHODS AND APPARATUS TO PERFORM ERROR DETECTION AND/OR CORRECTION IN A MEMORY DEVICE

    公开(公告)号:US20200151056A1

    公开(公告)日:2020-05-14

    申请号:US16617411

    申请日:2017-06-27

    Abstract: An example apparatus to monitor memory includes an error manager to compare a first memory location of a first error in the memory to a plurality of memory locations in an error history log, the plurality of memory locations previously identified in the error history log based on errors detected in the memory locations, ones of the memory locations associated with corresponding counters that track the errors detected in the memory locations, and update a first one of the counters corresponding to the first memory location when a first address of the first memory location matches a second address of one of the memory locations in the error history log. The example apparatus further includes a command generator to transmit a command to an error corrector to perform error correction on the first memory location when the first one of the counters satisfies a threshold.

    Communication device and method for reducing interference

    公开(公告)号:US10608728B2

    公开(公告)日:2020-03-31

    申请号:US16080025

    申请日:2016-04-01

    Inventor: Fang Yuan

    Abstract: A communication device and a method for Orthogonal Frequency Division Multiplexing (OFDM) configured to receive a signal from a second device; perform a channel estimation on the signal, wherein the channel estimation comprises determining a channel path gain, a channel path delay, and at least one of a channel path angle of arrival (AoA) or a channel path angle of departure (AoD); determine an optimal analog beamforming direction based on the channel estimation; and communicating the data using the analog beamforming.

    Methods and apparatus to perform error detection and/or correction in a memory device

    公开(公告)号:US11080135B2

    公开(公告)日:2021-08-03

    申请号:US16617411

    申请日:2017-06-27

    Abstract: An example apparatus to monitor memory includes an error manager to compare a first memory location of a first error in the memory to a plurality of memory locations in an error history log, the plurality of memory locations previously identified in the error history log based on errors detected in the memory locations, ones of the memory locations associated with corresponding counters that track the errors detected in the memory locations, and update a first one of the counters corresponding to the first memory location when a first address of the first memory location matches a second address of one of the memory locations in the error history log. The example apparatus further includes a command generator to transmit a command to an error corrector to perform error correction on the first memory location when the first one of the counters satisfies a threshold.

    Efficiently storing computer processor data structures in computer memory

    公开(公告)号:US11782645B2

    公开(公告)日:2023-10-10

    申请号:US17568956

    申请日:2022-01-05

    CPC classification number: G06F3/0659 G06F3/0604 G06F3/0631 G06F3/0673

    Abstract: Logic may store data structures for two or more processors in memory such as cache, system management memory, protected memory, or other memory. Logic may compress the data structures to be stored in the memory. Logic may determine a reference data structure, store the reference data structure in the memory, determine a difference between a data structure for a second processor and the reference data structure, and store the difference in the memory. Logic may store the difference in the memory within a data structure such as a linked list or a bitmap. Logic may decompress the difference by combining the difference with the reference data structure. Logic may expand the useable data region to include cache in the two or more processors. Logic may instruct two or more processors to store their processor data structures in their respective caches and perform initialization with the processor data structures.

    Efficiently storing computer processor data structures in computer memory

    公开(公告)号:US11288010B2

    公开(公告)日:2022-03-29

    申请号:US16638694

    申请日:2017-09-25

    Abstract: Logic may store data structures for two or more processors in memory such as cache, system management memory, protected memory, or other memory. Logic may compress the data structures to be stored in the memory. Logic may determine a reference data structure, store the reference data structure in the memory, determine a difference between a data structure for a second processor and the reference data structure, and store the difference in the memory. Logic may store the difference in the memory within a data structure such as a linked list or a bitmap. Logic may decompress the difference by combining the difference with the reference data structure. Logic may expand the useable data region to include cache in the two or more processors. Logic may instruct two or more processors to store their processor data structures in their respective caches and perform initialization with the processor data structures.

    Communication device and a method for determining an information from another apparatus

    公开(公告)号:US10608722B2

    公开(公告)日:2020-03-31

    申请号:US16080027

    申请日:2016-04-01

    Inventor: Fang Yuan

    Abstract: A communication device and a method for determining an information from a second device consisting of setting an initial beamforming pattern, wherein the initial beamforming pattern comprises a beamforming direction and a corresponding beamforming area for each of the plurality of antenna ports, comprising determining a concerned direction interval based on overlapping beamforming areas of adjacent pairs of the plurality of antenna ports; receiving a signal from the second device; measuring a signal gain from the signal on each of the plurality of antenna ports; determining which concerned direction interval the second device occupies based on an antenna port having the highest signal gain and on one of the adjacent pair of antenna ports to the antenna port having the highest signal gain having a higher signal gain; and determining the information from the second device based on the determined concerned direction interval.

    Communication device and a method for hybrid beamforming

    公开(公告)号:US10763931B2

    公开(公告)日:2020-09-01

    申请号:US16323777

    申请日:2016-09-27

    Inventor: Fang Yuan

    Abstract: A method and a communication device adapted for designing a hybrid beamforming (HB) precoding used in a mobile communication system with an antenna array, the method including aggregating spatial channel vectors received by the antenna array; performing a linear factorization of the aggregation; truncating the linear factorization to generate truncated channels; and designing the HB precoding based on the truncated channels, wherein the HB precoding includes a linearly generated analog beamforming component and a linearly generated digital beamforming component.

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