公开(公告)号：US20190205058A1

公开(公告)日：2019-07-04

申请号：US16326116

申请日：2016-09-28

Applicant: INTEL CORPORATION

Inventor： Yao JIN ,  Ashok RAJ ,  Anthony E.G. LUCK

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/0611 ,  G06F3/0631 ,  G06F3/067 ,  G06F11/00 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0862 ,  G06F13/1668 ,  G06F13/4027

Abstract: A computing system includes a plurality of nodes including a first node, the first node including at least one core, a memory controller, a node-track register (MSR), and a monitoring counter array including a plurality of counters. The memory controller is to access a plurality of bits of the node-track MSR to determine a subset of nodes to be tracked, wherein the subset of nodes includes the first node and a second node. The memory controller is further to allocate a first counter of the plurality of counters to track memory requests sent to a local system memory by the first node; and allocate a second counter of the plurality of counters to track a memory response associated with a memory request sent by the first node to the second node.