公开(公告)号：US20190324790A1

公开(公告)日：2019-10-24

申请号：US16469278

申请日：2016-12-16

Applicant: INTEL CORPORATION

Inventor： Tianyou Li ,  Shu Xu ,  Jinkui Ren ,  Zidong Jiang ,  Weiliang Lin ,  Chaobo Zhu ,  Yong Hu

IPC: G06F9/455 ,  G06F9/38

Abstract: In one example, a system for executing applications can include a main processor to initialize a virtual machine to execute an application. The main processor can also determine a main utilization indicator of the main processor is above a threshold and an auxiliary utilization indicator of an auxiliary processor is below a threshold, wherein the auxiliary processor is based on an auxiliary instruction set architecture. Additionally, the main processor can transmit an instruction from the application to the auxiliary processor for execution and update context data for the application in response to receiving an execution result from the auxiliary processor.

公开(公告)号：US10802979B2

公开(公告)日：2020-10-13

申请号：US16473588

申请日：2017-01-27

Applicant: Intel Corporation

Inventor： Shu Xu ,  Tianyou Li ,  Zidong Jiang ,  Weiliang Lion Lin ,  Jinkui Ren ,  Chaobo Zhu ,  Xiaokang Qin

IPC: G06F12/10 ,  G06F12/0891 ,  G06F12/06 ,  G06F12/0804 ,  G06F17/11

Abstract: Systems and techniques for dynamic code execution location in heterogeneous memory are described herein. In an system having a first class of memory and second class of memory that are both byte-addressable, an interpreter may be initialized to execute a program from the first class of memory. The initialization may include locating an Interpreter Routine Address Table (IRIT) in the second class of memory and creating counters for routines in the IRIT. A counter for a routine may be modified as it is referenced from the IRIT during execution. The routine may be moved from the first class of memory to the second class of memory in response to the counter passing a threshold. An entry in the IRIT for the routine may be updated with an address in the second class of memory corresponding to the routine.

公开(公告)号：US20220075639A1

公开(公告)日：2022-03-10

申请号：US17405857

申请日：2021-08-18

Applicant: Intel Corporation

Inventor： Tianyou Li ,  Shu Xu ,  Jinkui Ren ,  Zidong Jiang ,  Weiliang Lin ,  Chaobo Zhu ,  Yong Hu

IPC: G06F9/455 ,  G06F9/38

Abstract: In one example, a system for executing applications can include a main processor to initialize a virtual machine to execute an application. The main processor can also determine a main utilization indicator of the main processor is above a threshold and an auxiliary utilization indicator of an auxiliary processor is below a threshold, wherein the auxiliary processor is based on an auxiliary instruction set architecture. Additionally, the main processor can transmit an instruction from the application to the auxiliary processor for execution and update context data for the application in response to receiving an execution result from the auxiliary processor.

公开(公告)号：US11099879B2

公开(公告)日：2021-08-24

申请号：US16469278

申请日：2016-12-16

Applicant: INTEL CORPORATION

Inventor： Tianyou Li ,  Shu Xu ,  Jinkui Ren ,  Zidong Jiang ,  Weiliang Lin ,  Chaobo Zhu ,  Yong Hu

IPC: G06F9/455 ,  G06F9/38

Abstract: In one example, a system for executing applications can include a main processor to initialize a virtual machine to execute an application. The main processor can also determine a main utilization indicator of the main processor is above a threshold and an auxiliary utilization indicator of an auxiliary processor is below a threshold, wherein the auxiliary processor is based on an auxiliary instruction set architecture. Additionally, the main processor can transmit an instruction from the application to the auxiliary processor for execution and update context data for the application in response to receiving an execution result from the auxiliary processor.

公开(公告)号：US12067412B2

公开(公告)日：2024-08-20

申请号：US17405857

申请日：2021-08-18

Applicant: Intel Corporation

Inventor： Tianyou Li ,  Shu Xu ,  Jinkui Ren ,  Zidong Jiang ,  Weiliang Lin ,  Chaobo Zhu ,  Yong Hu

IPC: G06F9/455 ,  G06F9/38

CPC classification number: G06F9/45558 ,  G06F9/3838 ,  G06F2009/45562

Abstract: In one example, a system for executing applications can include a main processor to initialize a virtual machine to execute an application. The main processor can also determine a main utilization indicator of the main processor is above a threshold and an auxiliary utilization indicator of an auxiliary processor is below a threshold, wherein the auxiliary processor is based on an auxiliary instruction set architecture. Additionally, the main processor can transmit an instruction from the application to the auxiliary processor for execution and update context data for the application in response to receiving an execution result from the auxiliary processor.

公开(公告)号：US20190332545A1

公开(公告)日：2019-10-31

申请号：US16473588

申请日：2017-01-27

Applicant: Intel Corporation

Inventor： Shu Xu ,  Tianyou Li ,  Zidong Jiang ,  Weiliang Lion Lin ,  Jinkui Ren ,  Chaobo Zhu ,  Xiaokang Qin

IPC: G06F12/0891 ,  G06F12/0804 ,  G06F12/06 ,  G06F17/11

Abstract: Systems and techniques for dynamic code execution location in heterogeneous memory are described herein. In an system having a first class of memory and second class of memory that are both byte-addressable, an interpreter may be initialized to execute a program from the first class of memory. The initialization may include locating an Interpreter Routine Address Table (IRIT) in the second class of memory and creating counters for routines in the IRIT. A counter for a routine may be modified as it is referenced from the IRIT during execution. The routine may be moved from the first class of memory to the second class of memory in response to the counter passing a threshold. An entry in the IRIT for the routine may be updated with an address in the second class of memory corresponding to the routine.

公开(公告)号：US20180113794A1

公开(公告)日：2018-04-26

申请号：US15569331

申请日：2015-06-10

Applicant: Intel Corporation

Inventor： Jin Yang ,  Junchao Han ,  Zidong Jiang ,  Yongnian Le

IPC: G06F11/36 ,  G06F9/54

CPC classification number: G06F11/3668 ,  G06F8/447 ,  G06F9/54 ,  G06T11/00

Abstract: Various systems and methods for analyzing WebGL applications are described herein. A system comprises a recorder service module to intercept a plurality of graphics application programming interface (API) function calls, each of the plurality of graphics API functions calls having an associated execution context; a command translator module to translate the plurality of graphics API functions calls to a set of generic API invocations; a code generator module to generate executable code from the set of generic API invocations; and a replayer service module to test the executable code.