公开(公告)号：US10567074B2

公开(公告)日：2020-02-18

申请号：US15759745

申请日：2016-04-01

Applicant: INTEL IP CORPORATION

Inventor： Sabine Roessel ,  Holger Neuhaus ,  Yeong-Sun Hwang ,  Bertram Gunzelmann ,  Andreas Menkhoff ,  Elmar Wagner ,  Jong-Kae Fwu ,  Xiangyang Zhuang

IPC: H04B7/26 ,  H04L5/14 ,  H04L27/26 ,  H04L5/00 ,  H04W72/04

Abstract: Methods and apparatus for communicating in a wireless network including apparatus comprising transceiver circuitry to send and receive data in a plurality of time periods, defined by a time division duplex (TDD) time grid, to another entity, the plurality of time periods corresponding to a plurality of orthogonal frequency division multiplexing (OFDM) symbols and the transceiver circuitry being operable to switch from receive mode to transmit mode and/or from transmit mode to receive mode according to a flexible uplink and downlink allocation of the plurality of time periods; and baseband circuitry coupled to the transceiver circuitry to control the transceiver circuitry to switch during a switching interval embedded within a time period corresponding to an OFDM symbol of the plurality of OFDM symbols.

公开(公告)号：US10455511B2

公开(公告)日：2019-10-22

申请号：US14872015

申请日：2015-09-30

Applicant: Intel IP Corporation

Inventor： Andreas Menkhoff

IPC: H04W52/02 ,  H04W52/32

Abstract: Described herein are architectures, platforms and methods for implementing scalable power in a wireless device. Multiple radio access technology architectures running different operating clock frequencies are supported by providing a scaled static clock frequency and dynamic clock frequencies by dynamically switching parallel paths of processing resources.

公开(公告)号：US20190036486A1

公开(公告)日：2019-01-31

申请号：US16140991

申请日：2018-09-25

Applicant: Intel IP Corporation

Inventor： Stephan Henzler ,  Andreas Menkhoff ,  Thomas Eichler ,  Wolfgang Walthes ,  Alexander Belitzer ,  Yifan Wang

IPC: H03F1/02 ,  H03M1/66 ,  H03F3/24 ,  H03F3/189 ,  H03F3/19 ,  H03F3/21 ,  H03F3/68 ,  H02M3/07 ,  H02M3/158

Abstract: An envelope tracking system for controlling a power amplifier supply voltage includes envelope circuitry and a feed forward digital to analog converter (DAC) circuitry. The envelope circuitry is configured to generate a target envelope signal based on a selected power amplifier supply voltage. The feed forward DAC circuitry includes a voltage source circuitry and a selector circuitry. The voltage source circuitry is configured to generate a plurality of voltages. The selector circuitry is configured to select one of the plurality of voltages based at least on the target envelope signal. The feed forward DAC circuitry is configured to provide the selected voltage to a supply voltage input of a power amplifier that amplifies a radio frequency (RF) transmit signal.

公开(公告)号：US20180167056A1

公开(公告)日：2018-06-14

申请号：US15811851

申请日：2016-06-08

Applicant: Intel IP Corporation

Inventor： Thomas Bauernfeind ,  Andreas Menkhoff ,  Michael Bruennert

IPC: H03H17/02 ,  H03H17/00 ,  H03H17/06

CPC classification number: H03H17/0291 ,  H03F2200/336 ,  H03H17/0018 ,  H03H17/0635

Abstract: An apparatus for shifting a digital signal having a first sample rate by a shift time to provide a shifted signal having a second sample rate is provided. The apparatus includes a sample rate converter configured to provide a value of an interpolated signal at a compensated sample time as a sample of the shifted signal, the interpolated signal being based on the digital signal. The sample rate converter is configured to modify a time interval between a sample time of the digital signal and the compensated sample time based on the shift time.

公开(公告)号：US20150365113A1

公开(公告)日：2015-12-17

申请号：US14303945

申请日：2014-06-13

Applicant: Intel IP Corporation

Inventor： Andreas Menkhoff ,  Michael Bruennert ,  Markus Schimper

IPC: H04B1/04 ,  H04L27/20

CPC classification number: H04B1/0475 ,  H04L27/20 ,  H04L27/361

Abstract: A modulator and associated method includes a calculation block configured to receive a plurality of digital samples of a modulated baseband signal, and determine time instances associated with predetermined phase crossings of the modulated baseband signal. The modulator further includes a converter circuit configured to generate a data dependent clock signal having rising and falling edges associated with the determined time instances, and a digital to analog converter configured to receive the data dependent clock signal and generate a square wave output signal having transition times associated with the generated data dependent clock signal.

Abstract translation: 调制器和相关联的方法包括被配置为接收调制基带信号的多个数字样本的计算块，并且确定与调制基带信号的预定相位相关联的时间实例。 调制器还包括转换器电路，其被配置为产生具有与所确定的时间实例相关联的上升沿和下降沿的数据相关时钟信号，以及数模转换器，被配置为接收依赖于数据的时钟信号并产生具有转换的方波输出信号 与产生的数据相关时钟信号相关联的时间。

公开(公告)号：US20200077341A1

公开(公告)日：2020-03-05

申请号：US16542821

申请日：2019-08-16

Applicant: Intel IP Corporation

Inventor： Andreas Menkhoff

IPC: H04W52/02 ,  H04W52/32

Abstract: Described herein are architectures, platforms and methods for implementing scalable power in a wireless device. Multiple radio access technology architectures running different operating clock frequencies are supported by providing a scaled static clock frequency and dynamic clock frequencies by dynamically switching parallel paths of processing resources.

公开(公告)号：US20200044626A1

公开(公告)日：2020-02-06

申请号：US16543756

申请日：2019-08-19

Applicant: Intel IP Corporation

Inventor： Thomas Bauernfeind ,  Andreas Menkhoff ,  Michael Bruennert

IPC: H03H17/02 ,  H03H17/06 ,  H03H17/00

Abstract: An apparatus for shifting a digital signal having a first sample rate by a shift time to provide a shifted signal having a second sample rate is provided. The apparatus includes a sample rate converter configured to provide a value of an interpolated signal at a compensated sample time as a sample of the shifted signal, the interpolated signal being based on the digital signal. The sample rate converter is configured to modify a time interval between a sample time of the digital signal and the compensated sample time based on the shift time.

公开(公告)号：US20190028321A1

公开(公告)日：2019-01-24

申请号：US15752263

申请日：2015-09-25

Applicant: Intel IP Corporation

Inventor： Andreas Menkhoff

IPC: H04L27/36 ,  H04B1/04

Abstract: A method for approximating a first signal having a first oscillation period within a quantized time interval using a second signal is provided. The second signal has a second oscillation period. The method includes calculating a phase offset of the first signal at at least one position within the quantized time interval. Further, the method comprises shifting the second signal within the quantized time interval until a phase offset of the second signal at the at least one position satisfies a quality criterion related to the phase offset of the first signal.

公开(公告)号：US20190028319A1

公开(公告)日：2019-01-24

申请号：US15752261

申请日：2015-09-25

Applicant: Intel IP Corporation

Inventor： Andreas Menkhoff

IPC: H04L27/36 ,  H04B1/04

CPC classification number: H04L27/36 ,  H04B1/04 ,  H04L27/0008

Abstract: An apparatus for generating a radio frequency signal is provided. The apparatus includes a modulator configured to generate the radio frequency signal based on an input signal. Further, the apparatus includes a controller configured to control the modulator to generate the radio frequency signal using polar modulation, if the input signal has a first characteristic. The controller is configured to control the modulator to generate the radio frequency signal using quadrature modulation, if the input signal has a different second characteristic.

公开(公告)号：US10044322B2

公开(公告)日：2018-08-07

申请号：US15609041

申请日：2017-05-31

Applicant: Intel IP Corporation

Inventor： Andreas Menkhoff ,  Zdravko Boos

IPC: H04B1/40 ,  H03D7/16 ,  H04B1/00 ,  H04B1/403 ,  H03J1/00 ,  H03B21/02 ,  G06F1/02

Abstract: A radio frequency signal synthesizer circuit includes a digital to analog converter configured to generate an analog output signal for each clock cycle of a clock signal to provide the radio frequency signal and a controlled oscillator to generate the clock signal. The controlled oscillator is configured to vary a cycle time of the clock signal for a radio frequency signal in a first frequency range in a first operation mode or to maintain a constant cycle time for a radio frequency signal in a second frequency range in a second operation mode, the second frequency range being different than the first frequency range.