公开(公告)号：US10531561B2

公开(公告)日：2020-01-07

申请号：US16285437

申请日：2019-02-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kathleen Ann Fadden ,  James A. Busby ,  David C. Long ,  John R. Dangler ,  Alexandra Echegaray ,  Michael J. Fisher ,  William Santiago-Fernandez

IPC: H05K5/00 ,  H05K1/02 ,  H05K1/18 ,  H05K1/11 ,  H05K3/00

Abstract: Tamper-respondent assemblies and fabrication methods are provided which incorporate enclosure-to-circuit board protection. The tamper-respondent assemblies include a circuit board, and an enclosure mounted to the circuit board along an enclosure-to-board interface. The enclosure facilitates enclosing at least one electronic component coupled to the circuit board within a secure volume. A tamper-respondent electronic circuit structure facilitates defining the secure volume, and includes one or more tamper-detect circuits including at least one conductive trace disposed, at least in part, within the enclosure-to-board interface. The conductive trace(s) includes stress rise regions to facilitate tamper-detection at the enclosure-to-board interface. An adhesive is provided to secure the enclosure to the circuit board. The adhesive contacts, at least in part, the conductive trace(s) of the tamper-detect circuit(s) at the enclosure-to-board interface, including at the stress rise regions of the conductive trace(s).

公开(公告)号：US10306753B1

公开(公告)日：2019-05-28

申请号：US15901985

申请日：2018-02-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kathleen Ann Fadden ,  James A. Busby ,  David C. Long ,  John R. Dangler ,  Alexandra Echegaray ,  Michael J. Fisher ,  William Santiago-Fernandez

IPC: H03K5/00 ,  H05K1/02 ,  H05K1/18 ,  H05K1/11 ,  H05K3/00 ,  H05K5/00

Abstract: Tamper-respondent assemblies and fabrication methods are provided which incorporate enclosure-to-circuit board protection. The tamper-respondent assemblies include a circuit board, and an enclosure mounted to the circuit board along an enclosure-to-board interface. The enclosure facilitates enclosing at least one electronic component coupled to the circuit board within a secure volume. A tamper-respondent electronic circuit structure facilitates defining the secure volume, and includes one or more tamper-detect circuits including at least one conductive trace disposed, at least in part, within the enclosure-to-board interface. The conductive trace(s) includes stress rise regions to facilitate tamper-detection at the enclosure-to-board interface. An adhesive is provided to secure the enclosure to the circuit board. The adhesive contacts, at least in part, the conductive trace(s) of the tamper-detect circuit(s) at the enclosure-to-board interface, including at the stress rise regions of the conductive trace(s).

公开(公告)号：US10042972B2

公开(公告)日：2018-08-07

申请号：US15474244

申请日：2017-03-30

Applicant: International Business Machines Corporation

Inventor： Alexandra Echegaray ,  Bernd Kemmier ,  Jesse P. Surprise ,  Stephen K. Szulewski

IPC: G06F17/50 ,  H01L23/538 ,  H04B3/462

Abstract: A method for assigning nets to wiring planes for generating a chip design includes executing, by a computer, a zero wire load timing session for a placed but unbufferred chip design. All nets of the chip design are set to a single wide wiring track without wiring plane assignments. A delta time delay is added to each sink of each of the nets to represent an estimated time of flight (TOF) delay. The nets wiring plane or width type for a particular pin is upgraded to a type having improved TOF characteristics. Each of the nets are compared against new predetermined slack and distance targets and new assigned wiring plane or width type determined to consume additional wiring track resources, and based on results, the upgrade is repeated or a design for session timing state for the nets is output to represent the unbufferred chip design.

公开(公告)号：US11083082B2

公开(公告)日：2021-08-03

申请号：US16567034

申请日：2019-09-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kathleen Ann Fadden ,  James A. Busby ,  David C. Long ,  John R. Dangler ,  Alexandra Echegaray ,  Michael J. Fisher ,  William Santiago-Fernandez

IPC: H05K5/00 ,  H05K1/02 ,  H05K1/18 ,  H05K1/11 ,  G06F21/00 ,  G06F21/86 ,  H05K5/02 ,  H05K3/00

Abstract: Tamper-respondent assemblies and fabrication methods are provided which incorporate enclosure-to-circuit board protection. The tamper-respondent assemblies include a circuit board, and an enclosure mounted to the circuit board along an enclosure-to-board interface. The enclosure facilitates enclosing at least one electronic component coupled to the circuit board within a secure volume. A tamper-respondent electronic circuit structure facilitates defining the secure volume, and includes one or more tamper-detect circuits including at least one conductive trace disposed, at least in part, within the enclosure-to-board interface. The conductive trace(s) includes stress rise regions to facilitate tamper-detection at the enclosure-to-board interface. An adhesive is provided to secure the enclosure to the circuit board. The adhesive contacts, at least in part, the conductive trace(s) of the tamper-detect circuit(s) at the enclosure-to-board interface, including at the stress rise regions of the conductive trace(s).

公开(公告)号：US20170212976A1

公开(公告)日：2017-07-27

申请号：US15474244

申请日：2017-03-30

Applicant: International Business Machines Corporation

Inventor： Alexandra Echegaray ,  Bernd Kemmier ,  Jesse P. Surprise ,  Stephen K. Szulewski

IPC: G06F17/50 ,  H01L23/538 ,  H04B3/462

CPC classification number: G06F17/5077 ,  G06F17/5031 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/78 ,  G06F2217/84 ,  H01L23/5382 ,  H04B3/462

Abstract: A method for assigning nets to wiring planes for generating a chip design includes executing, by a computer, a zero wire load timing session for a placed but unbufferred chip design. All nets of the chip design are set to a single wide wiring track without wiring plane assignments. A delta time delay is added to each sink of each of the nets to represent an estimated time of flight (TOF) delay. The nets wiring plane or width type for a particular pin is upgraded to a type having improved TOF characteristics. Each of the nets are compared against new predetermined slack and distance targets and new assigned wiring plane or width type determined to consume additional wiring track resources, and based on results, the upgrade is repeated or a design for session timing state for the nets is output to represent the unbufferred chip design.

公开(公告)号：US09684756B1

公开(公告)日：2017-06-20

申请号：US15005734

申请日：2016-01-25

Applicant: International Business Machines Corporation

Inventor： Alexandra Echegaray ,  Bernd Kemmler ,  Jesse P. Surprise ,  Stephen K. Szulewski

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5031 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/78 ,  G06F2217/84 ,  H01L23/5382 ,  H04B3/462

Abstract: Nets are assigned to wiring planes for generating a chip design. A computer is caused to execute a zero wire load timing session for a placed but unbufferred chip design. All nets of the chip design are set to a single wide wiring track without wiring plane assignments. A delta time delay is added to each sink of each of the nets to represent an estimated time of flight (TOF) delay. The nets wiring plane or width type for a particular pin is upgraded to a type having improved TOF characteristics. Each of the nets are compared against new predetermined slack and distance targets and new assigned wiring plane or width type determined to consume additional wiring track resources, and based on results, the upgrade is repeated or a design for session timing state for the nets is output to represent the unbufferred chip design.