公开(公告)号：US11663381B2

公开(公告)日：2023-05-30

申请号：US17468304

申请日：2021-09-07

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Stephen Gerard Shuma ,  Ali S. El-Zein ,  Wolfgang Roesner ,  Viresh Paruthi ,  Benedikt Geukes ,  Klaus-Dieter Schubert ,  Birgit Schubert ,  Stephen John Barnfield ,  Derek E. Williams

IPC分类号： G06F30/30 ,  G06F30/327 ,  G06F30/31 ,  G06F30/323

CPC分类号： G06F30/327 ,  G06F30/31 ,  G06F30/323

摘要： A processor receives, as input, a first hardware description language (HDL) file defining an entity of a modular circuit design. The first HDL file instantiates, by a storage element declaration in a hardware description language, a storage element within the entity. The first HDL file omits a port map for the storage element. Based on the first HDL file, the processor automatically fully elaborates a port map for the storage element. The processor stores, in data storage, a derived second HDL file defining the entity and including the port map.

公开(公告)号：US20230075770A1

公开(公告)日：2023-03-09

申请号：US17468304

申请日：2021-09-07

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Stephen Gerard Shuma ,  Ali S. El-Zein ,  Wolfgang Roesner ,  Viresh Paruthi ,  Benedikt Geukes ,  Klaus-Dieter Schubert ,  Birgit Schubert ,  Stephen John Barnfield ,  Derek E. Williams

IPC分类号： G06F30/327 ,  G06F30/323 ,  G06F30/31

摘要： A processor receives, as input, a first hardware description language (HDL) file defining an entity of a modular circuit design. The first HDL file instantiates, by a storage element declaration in a hardware description language, a storage element within the entity. The first HDL file omits a port map for the storage element. Based on the first HDL file, the processor automatically fully elaborates a port map for the storage element. The processor stores, in data storage, a derived second HDL file defining the entity and including the port map.