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公开(公告)号：US20230074528A1
公开(公告)日：2023-03-09
申请号：US17468278
申请日：2021-09-07
发明人： Ali S. El-Zein , Wolfgang Roesner , Viresh Paruthi , Stephen Gerard Shuma , Stephen John Barnfield , Maya Safieddine , Benedikt Geukes , Klaus-Dieter Schubert , Gabor Drasny
IPC分类号： G06F30/327 , G06F30/3308
摘要： A first plurality of hardware description language (HDL) files defines a first scope of design forming only a subset of a larger hierarchical integrated circuit design. Technology-specific structures specific to a physical implementation are incorporated in the first scope of design. A second plurality of HDL files defining a first design entity that is at the first scope of design and that includes the technology-specific structures is generated. A third plurality of HDL files defining a second scope of design for the hierarchical integrated circuit design that is larger than and includes the first scope of design is formed. The third plurality of HDL files is processed to form a representation of the second scope of design. Processing the third plurality of HDL files includes replacing a second design entity in the second scope of design lacking at least some technology-specific structures with the first design entity.
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公开(公告)号：US20230072735A1
公开(公告)日：2023-03-09
申请号：US17468340
申请日：2021-09-07
发明人： Ali S. El-Zein , Wolfgang Roesner , Stephen Gerard Shuma , Robert Lowell Kanzelman , Michael Hemsley Wood , Chung-Lung K. Shum , Gabor Bobok , Robert James Shadowen , Viresh Paruthi , Derek E. Williams
IPC分类号： G06F30/323 , G06F30/3323 , G06F30/327
摘要： A processor receives an expression of design refinement intent with regard to an entity forming a part of a modular circuit design. The entity is defined by a hardware description language (HDL) file, and the expression of design refinement intent identifies an intent region within an implementation of the entity and specifies replacement logic for the region. Based on the expression of design refinement intent, the processor automatically modifies the HDL file by replacing logic within the intent region with the replacement logic. The processor then performs logical synthesis to generate a gate list representation of the modular circuit design as modified.
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公开(公告)号：US20230075565A1
公开(公告)日：2023-03-09
申请号：US17468243
申请日：2021-09-07
发明人： Wolfgang Roesner , Ali S. El-Zein , Viresh Paruthi , Stephen Gerard Shuma , Stephen John Barnfield , Alvan Wing Ng , Robert James Shadowen
IPC分类号： G06F30/394 , G06F30/333
摘要： Based on a directive in a control file, a processor pre-routes, within a hierarchical integrated circuit design, a signal through one or more levels of design hierarchy between a signal source at a higher level of the design hierarchy and an entity instance at a lower level of the design hierarchy. The processor processes entity instances in the design hierarchy in a bottom-up manner to insert technology-specific structures into the hierarchical integrated circuit design. During the processing, the processor inserts into a particular entity instance of the design hierarchy a technology-specific structure and connects the technology-specific structure to the signal pre-routed to the particular entity instance by the pre-routing.
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公开(公告)号：US12050852B2
公开(公告)日：2024-07-30
申请号：US17468243
申请日：2021-09-07
发明人： Wolfgang Roesner , Ali S. El-Zein , Viresh Paruthi , Stephen Gerard Shuma , Stephen John Barnfield , Alvan Wing Ng , Robert James Shadowen
IPC分类号： G06F30/394 , G06F30/333
CPC分类号： G06F30/394 , G06F30/333
摘要： Based on a directive in a control file, a processor pre-routes, within a hierarchical integrated circuit design, a signal through one or more levels of design hierarchy between a signal source at a higher level of the design hierarchy and an entity instance at a lower level of the design hierarchy. The processor processes entity instances in the design hierarchy in a bottom-up manner to insert technology-specific structures into the hierarchical integrated circuit design. During the processing, the processor inserts into a particular entity instance of the design hierarchy a technology-specific structure and connects the technology-specific structure to the signal pre-routed to the particular entity instance by the pre-routing.
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公开(公告)号：US11663381B2
公开(公告)日：2023-05-30
申请号：US17468304
申请日：2021-09-07
发明人： Stephen Gerard Shuma , Ali S. El-Zein , Wolfgang Roesner , Viresh Paruthi , Benedikt Geukes , Klaus-Dieter Schubert , Birgit Schubert , Stephen John Barnfield , Derek E. Williams
IPC分类号： G06F30/30 , G06F30/327 , G06F30/31 , G06F30/323
CPC分类号： G06F30/327 , G06F30/31 , G06F30/323
摘要： A processor receives, as input, a first hardware description language (HDL) file defining an entity of a modular circuit design. The first HDL file instantiates, by a storage element declaration in a hardware description language, a storage element within the entity. The first HDL file omits a port map for the storage element. Based on the first HDL file, the processor automatically fully elaborates a port map for the storage element. The processor stores, in data storage, a derived second HDL file defining the entity and including the port map.
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公开(公告)号：US20230075770A1
公开(公告)日：2023-03-09
申请号：US17468304
申请日：2021-09-07
发明人： Stephen Gerard Shuma , Ali S. El-Zein , Wolfgang Roesner , Viresh Paruthi , Benedikt Geukes , Klaus-Dieter Schubert , Birgit Schubert , Stephen John Barnfield , Derek E. Williams
IPC分类号： G06F30/327 , G06F30/323 , G06F30/31
摘要： A processor receives, as input, a first hardware description language (HDL) file defining an entity of a modular circuit design. The first HDL file instantiates, by a storage element declaration in a hardware description language, a storage element within the entity. The first HDL file omits a port map for the storage element. Based on the first HDL file, the processor automatically fully elaborates a port map for the storage element. The processor stores, in data storage, a derived second HDL file defining the entity and including the port map.
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公开(公告)号：US20230070516A1
公开(公告)日：2023-03-09
申请号：US17468319
申请日：2021-09-07
发明人： Ali S. El-Zein , Viresh Paruthi , Alvan Wing Ng , Benedikt Geukes , Klaus-Dieter Schubert , Robert Alan Cargnoni , Michael Hemsley Wood , Stephen Gerard Shuma , Wolfgang Roesner , Chung-Lung K. Shum , Edward Armayor McQuade , Derek E. Williams
IPC分类号： G06F30/327 , G06F30/3308
摘要： A first plurality of hardware description language (HDL) files describe a hierarchical integrated circuit design utilizing a simplified HDL syntax that omits specification of logical clock connections for at least some entities in the hierarchical integrated circuit design. The hierarchical integrated circuit design as described by the first plurality of HDL files is processed to automatically add logical clock connections for entities in the hierarchical integrated circuit design for which specification of logical clock connections are omitted in the first plurality of HDL files. Based on the processing, a second plurality of HDL files defining the hierarchical integrated circuit design is generated.
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