公开(公告)号：US11797270B2

公开(公告)日：2023-10-24

申请号：US17350550

申请日：2021-06-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cedric Lichtenau ,  Jonathan D. Bradbury ,  Laith M. AlBarakat

IPC: G06F7/544 ,  G06F17/18 ,  G06N3/063

CPC classification number: G06F7/544 ,  G06F17/18 ,  G06N3/063

Abstract: An indication of a function to be executed is obtained, in which the function is one function of an instruction and configured to perform multiple operations. A determination is made of an operation of the multiple operations to be performed, and a set of function-specific parameters is validated using a set of values and a corresponding set of relationships. The set of values and corresponding set of relationships are based on the operation to be performed. One set of values and corresponding set of relationships are to be used for the operation to be performed, and another set of values and corresponding set of relationships are to be used for another operation of the multiple operations.

公开(公告)号：US20230289138A1

公开(公告)日：2023-09-14

申请号：US17653946

申请日：2022-03-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Petra Leber ,  Kerstin Claudia Schelm ,  Cedric Lichtenau ,  Stefan Payer ,  Michael Klein ,  Silvia Melitta Mueller

IPC: G06F7/48

CPC classification number: G06F7/48

Abstract: A hardware device is provided to perform a plurality of operations to convert an input value directly from one format to another format. The hardware device is to perform the plurality of operations based on execution of an instruction. The plurality of operations includes scaling the input value to provide a scaled result and converting the scaled result from the one format to provide a converted result in the other format. The scaling and converting are to be performed as part of executing the instruction. The converted result in the other format is provided to be used in processing within the computing environment.

公开(公告)号：US11669331B2

公开(公告)日：2023-06-06

申请号：US17350393

申请日：2021-06-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Laith M. AlBarakat ,  Jonathan D. Bradbury ,  Timothy Slegel ,  Cedric Lichtenau ,  Simon Weishaupt ,  Anthony Saporito

IPC: G06F9/38 ,  G06N3/02 ,  G06N3/10 ,  G06F9/30 ,  G06F9/54

CPC classification number: G06F9/3838 ,  G06F9/3877 ,  G06N3/02

Abstract: A first processor processes an instruction configured to perform a plurality of functions. The plurality of functions includes one or more functions to operate on one or more tensors. A determination is made of a function of the plurality of functions to be performed. The first processor provides to a second processor information related to the function. The second processor is to perform the function. The first processor and the second processor share memory providing memory coherence.

公开(公告)号：US11620153B2

公开(公告)日：2023-04-04

申请号：US16266752

申请日：2019-02-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cedric Lichtenau ,  Jonathan D. Bradbury ,  Reid Copeland ,  Petra Leber

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/30

Abstract: Instruction interrupt suppression for an overflow condition. An instruction is executed, and a determination is made that an overflow condition occurred. Based on a per-instruction overflow interrupt indicator being set to a defined value, interrupt processing for the overflow condition is performed, and based on the per-instruction overflow interrupt indicator being set to another defined value, the interrupt processing for the overflow condition is bypassed.

公开(公告)号：US20220413867A1

公开(公告)日：2022-12-29

申请号：US17350467

申请日：2021-06-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Laith M. AlBarakat ,  Jonathan D. Bradbury ,  Timothy Slegel ,  Cedric Lichtenau ,  Joachim von Buttlar

IPC: G06F9/38 ,  G06N3/04

Abstract: An exception summary is provided for an invalid value detected during instruction execution. An indication that a value determined to be invalid was included in input data to a computation of one or more computations or in output data resulting from the one or more computations is obtained. The value is determined to be invalid due to one exception of a plurality of exceptions. Based on obtaining the indication that the value is determined to be invalid, a summary indicator is set. The summary indicator represents the plurality of exceptions collectively.

公开(公告)号：US20220405555A1

公开(公告)日：2022-12-22

申请号：US17350619

申请日：2021-06-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cedric Lichtenau ,  Kailash Gopalakrishnan ,  Vijayalakshmi Srinivasan ,  Sunil K. Shukla ,  Swagath Venkataramani

IPC: G06N3/063

Abstract: A combined function specified by an instruction is performed. The combined function includes a plurality of operations performed as part of one invocation of the combined function. The performing the combined function includes performing a convolution using a first tensor and a second tensor to obtain one or more intermediate results, in which the second tensor includes an adjusted weight tensor created using a plurality of multipliers. Values of a bias tensor are added to the one or more intermediate results to obtain one or more combined function results for the combined function.

公开(公告)号：US11099602B2

公开(公告)日：2021-08-24

申请号：US16398793

申请日：2019-04-30

Applicant: International Business Machines Corporation

Inventor： Razvan Peter Figuli ,  Cedric Lichtenau ,  Stefan Payer ,  Michael Klein

IPC: G06F1/14 ,  H03K21/10 ,  H03K19/20

Abstract: A method includes obtaining a trigger signal directed to a component in a subset of components of an electronic circuit, and activating a clock corresponding with the subset of components of the electronic circuit for a preliminary period in response to the trigger signal. An active period is determined based on the trigger signal. The clock remains active for the active period. One of a timer or counter is initiated for the active period. A limit is defined for the one of the timer or counter. The active period is dynamically extended for a busy period after the one of the timer or counter is initiated. The clock is deactivated following the active period.

公开(公告)号：US11068541B2

公开(公告)日：2021-07-20

申请号：US16276712

申请日：2019-02-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cedric Lichtenau ,  Jonathan D. Bradbury ,  Eric M. Schwarz ,  Razvan Peter Figuli ,  Stefan Payer

IPC: G06F7/00 ,  G06F16/903 ,  G06F40/205 ,  G06F17/16

Abstract: An instruction is provided for performing a vector string search. The instruction to be processed is obtained, with the instruction being defined to be a string search instruction to locate occurrence of a substring within a string. The instruction is processed, with the processing including searching the string specified in one operand of the instruction using the substring specified in another operand of the instruction. Based on the searching locating a first full match of the substring within the string, a full match condition indication is returned with position of the first full match in the string, and based on the searching locating only a partial match of the substring at a termination of the string, a partial match condition indication is returned, with the position of the partial match in the string.

公开(公告)号：US20210042119A1

公开(公告)日：2021-02-11

申请号：US16536671

申请日：2019-08-09

Applicant: International Business Machines Corporation

Inventor： Petra Leber ,  Kerstin Claudia Schelm ,  Cedric Lichtenau ,  Michael Klein

IPC: G06F9/30 ,  G06F11/07

Abstract: An aspect includes generating a data result and a special case indicator based on an instruction and at least one input data operand. Outputting the data result to a processor core. Outputting the first condition code to the processor core prior to outputting the data result to the processor core. Generating a second condition code based on the data result and the special case indicator. Performing a check by comparing the first condition code and the second condition code and flagging an error to the processor core upon the first condition code being different from the second condition code.

公开(公告)号：US10739401B2

公开(公告)日：2020-08-11

申请号：US16017188

申请日：2018-06-25

Applicant: International Business Machines Corporation

Inventor： Satya R. S. Bhamidipati ,  Raghu G. Gopalakrishnasetty ,  Mary P. Kusko ,  Cedric Lichtenau

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/317 ,  G01R31/3183 ,  G01R31/3185 ,  G01R31/3187

Abstract: Aspects include a system having logic built-in self-test (LBIST) circuitry for use in an integrated circuit with scan chains. The system includes a pattern generator configured for generating scan-in test values for said scan chains; a signature register configured for collecting scan-out responses from said scan chains after a clock sequence; an on-product control generator configured for controlling at least one test parameter; one or more microcode array or memory elements configured to receive inputs to initialize fields in the microcode array or memory elements; and a test controller. The test controller includes a reader component configured for reading test parameters from a field of the microcode array or the memory elements; and a programming component configured for configuring the on-product control generator and the pattern generator with a LBIST pattern according to the read test parameters.