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公开(公告)号：US11663004B2
公开(公告)日：2023-05-30
申请号：US17186443
申请日：2021-02-26
发明人： Eric Mark Schwarz , Kerstin Claudia Schelm , Petra Leber , Silvia Melitta Mueller , Reid Copeland , Xin Guo , Cedric Lichtenau
CPC分类号： G06F9/30036 , G06F7/483 , G06F7/49947 , G06F9/3001 , G06F9/3555
摘要： An instruction to perform converting and scaling operations is provided. Execution of the instruction includes converting an input value in one format to provide a converted result in another format. The converted result is scaled to provide a scaled result. A result obtained from the scaled result is placed in a selected location. Further, an instruction to perform scaling and converting operations is provided. Execution of the instruction includes scaling an input value in one format to provide a scaled result and converting the scaled result from the one format to provide a converted result in another format. A result obtained from the converted result is placed in a selected location.
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2.发明授权Hybrid polymorphic inline cache and branch target buffer prediction units for indirect branch prediction for emulation environments 有权用于仿真环境的间接分支预测的混合多态内联高速缓存和分支目标缓冲区预测单元公开(公告)号：US09317292B2
公开(公告)日：2016-04-19
申请号：US14068044
申请日：2013-10-31
发明人： Carlos Cavanna , Reid Copeland , Chad McIntyre , Ali Sheikh
CPC分类号： G06F9/3806 , G06F9/30058 , G06F9/3848 , G06F9/455 , G06F12/0875 , G06F2212/452
摘要： Branch instructions are managed in an emulation environment that is executing a program. A plurality of slots in a Polymorphic Inline Cache is populated. A plurality of entries is populated in a branch target buffer residing within an emulated environment in which the program is executing. When an indirect branch instruction associated with the program is encountered, a target address associated with the instruction is identified from the indirect branch instruction. At least one address in each of the slots of the Polymorphic Inline Cache is compared to the target address associated with the indirect branch instruction. If none of the addresses in the slots of the Polymorphic Inline Cache matches the target address associated with the indirect branch instruction, the branch target buffer is searched to identify one of the entries in the branch target buffer that is associated with the target address of the indirect branch instruction.
摘要翻译： 分支指令在正在执行程序的仿真环境中进行管理。 填充多形体内联高速缓存中的多个时隙。 多个条目填充在驻留在程序正在执行的仿真环境中的分支目标缓冲器中。 当遇到与程序相关联的间接分支指令时，从间接分支指令识别与指令相关联的目标地址。 将多形态内联高速缓存的每个时隙中的至少一个地址与与间接分支指令相关联的目标地址进行比较。 如果多形态内联高速缓存的时隙中的任何地址都不匹配与间接分支指令相关联的目标地址，则搜索分支目标缓冲区以识别与目标地址相关联的分支目标缓冲器中的一个条目 间接分支指令。
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公开(公告)号：US11886848B2
公开(公告)日：2024-01-30
申请号：US17664969
申请日：2022-05-25
发明人： Toshihiko Koju , Reid Copeland , David Kevin Siegwart , Jordan Ryan Zannier , Allan H. Kielstra
IPC分类号： G06F8/41
摘要： A method, system, and computer-readable medium for binary translation cause a binary translator to combine raw binary code and compiler-produced metadata associated with a compiled program module. The binary translator is caused to further reconcile, using the compiler-produced metadata, original compiler-produced control flow information with how lower-level machine instructions comprise a control flow in the raw binary code, and original compiler-produced aliasing information with how lower-level machine instructions access the memory locations described by the aliasing information according to predetermined criteria. The binary translator further caused to prevent, copy propagation of values in temporary variables for decimal computations beyond offsets in the machine instructions where the temporary variables are killed. The binary translator further caused to remove identified dead store instructions, and to generate a new compiled program module comprising an optimized version of the compiled program module having strict compatibility to an original version of the compiled program module.
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公开(公告)号：US11620153B2
公开(公告)日：2023-04-04
申请号：US16266752
申请日：2019-02-04
摘要： Instruction interrupt suppression for an overflow condition. An instruction is executed, and a determination is made that an overflow condition occurred. Based on a per-instruction overflow interrupt indicator being set to a defined value, interrupt processing for the overflow condition is performed, and based on the per-instruction overflow interrupt indicator being set to another defined value, the interrupt processing for the overflow condition is bypassed.
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公开(公告)号：US11003453B2
公开(公告)日：2021-05-11
申请号：US16716916
申请日：2019-12-17
发明人： Carlos Cavanna , Reid Copeland , Chad McIntyre , Ali Sheikh
IPC分类号： G06F9/38 , G06F9/455 , G06F9/30 , G06F9/32 , G06F12/0875
摘要： Branch instructions are managed in an emulation environment that is executing a program. A plurality of slots in a Polymorphic Inline Cache is populated. A plurality of entries is populated in a branch target buffer residing within an emulated environment in which the program is executing. When an indirect branch instruction associated with the program is encountered, a target address associated with the instruction is identified from the indirect branch instruction. At least one address in each of the slots of the Polymorphic Inline Cache is compared to the target address associated with the indirect branch instruction. If none of the addresses in the slots of the Polymorphic Inline Cache matches the target address associated with the indirect branch instruction, the branch target buffer is searched to identify one of the entries in the branch target buffer that is associated with the target address of the indirect branch instruction.
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公开(公告)号：US10534612B2
公开(公告)日：2020-01-14
申请号：US15470972
申请日：2017-03-28
发明人： Carlos Cavanna , Reid Copeland , Chad McIntyre , Ali Sheikh
IPC分类号： G06F9/48 , G06F9/38 , G06F9/455 , G06F9/30 , G06F12/0875
摘要： Branch instructions are managed in an emulation environment that is executing a program. A plurality of slots in a Polymorphic Inline Cache is populated. A plurality of entries is populated in a branch target buffer residing within an emulated environment in which the program is executing. When an indirect branch instruction associated with the program is encountered, a target address associated with the instruction is identified from the indirect branch instruction. At least one address in each of the slots of the Polymorphic Inline Cache is compared to the target address associated with the indirect branch instruction. If none of the addresses in the slots of the Polymorphic Inline Cache matches the target address associated with the indirect branch instruction, the branch target buffer is searched to identify one of the entries in the branch target buffer that is associated with the target address of the indirect branch instruction.
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公开(公告)号：US11593080B1
公开(公告)日：2023-02-28
申请号：US17644813
申请日：2021-12-17
发明人： Jordan Ryan Zannier , Reid Copeland
IPC分类号： G06F8/41
摘要： Dataflow optimization by dead store elimination focusing on logically dividing a contiguous storage area into different portions by use to allow a different number and type of dataflow and dead store techniques on each portion. A first storage portion, containing the storage for control flow related metadata, is split from a remaining storage portion. Liveness analysis is executed on the first storage portion using bitvectors with each bit representing four bytes. The remaining storage portion, containing the temporary storage for computational values, is processed using a deadness-range-based dataflow analysis. IN and OUT sets for each basic block are generated by processing blocks GEN and KILL sets by performing a backwards intersection dataflow analysis. Stores that write to the set of dead ranges in the IN sets of blocks are eliminated as dead stores.
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公开(公告)号：US20220283818A1
公开(公告)日：2022-09-08
申请号：US17194740
申请日：2021-03-08
发明人： Eric Mark Schwarz , Stefan Payer , Petra Leber , Kerstin Claudia Schelm , Michael Klein , Timothy Slegel , Reid Copeland , Xin Guo
摘要： An instruction to perform an operation selected from a plurality of operations configured for the instruction is executed. The executing includes determining a value of a selected operand of the instruction. The determining the value is based on a control of the instruction and includes reading the selected operand of the instruction from a selected operand location to obtain the value of the selected operand, based on the control having a first value, and using a predetermined value as the value of the selected operand, based on the control having a second value. The value and another selected operand of the instruction are multiplied to obtain a product. An arithmetic operation is performed using the product and a chosen operand of the instruction to obtain an intermediate result. A result from the intermediate result is obtained and placed in a selected location.
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公开(公告)号：US20220276866A1
公开(公告)日：2022-09-01
申请号：US17186756
申请日：2021-02-26
发明人： Eric Mark Schwarz , Timothy Slegel , Jonathan D. Bradbury , Michael Klein , Reid Copeland , Xin Guo
IPC分类号： G06F9/30
摘要： Vector pack and unpack instructions are described. An instruction to perform a conversion between one decimal format and another decimal format is executed, in which the one decimal format or the other decimal format is a zoned decimal format. The executing includes obtaining a value from at least one register specified using the instruction. At least a portion of the value is converted from the one decimal format to the other decimal format different from the one decimal format to provide a converted result. A result obtained from the converted result is written into a single register specified using the instruction.
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公开(公告)号：US11531546B2
公开(公告)日：2022-12-20
申请号：US17194740
申请日：2021-03-08
发明人： Eric Mark Schwarz , Stefan Payer , Petra Leber , Kerstin Claudia Schelm , Michael Klein , Timothy Slegel , Reid Copeland , Xin Guo
摘要： An instruction to perform an operation selected from a plurality of operations configured for the instruction is executed. The executing includes determining a value of a selected operand of the instruction. The determining the value is based on a control of the instruction and includes reading the selected operand of the instruction from a selected operand location to obtain the value of the selected operand, based on the control having a first value, and using a predetermined value as the value of the selected operand, based on the control having a second value. The value and another selected operand of the instruction are multiplied to obtain a product. An arithmetic operation is performed using the product and a chosen operand of the instruction to obtain an intermediate result. A result from the intermediate result is obtained and placed in a selected location.
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