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    FLEXIBLE CONSTRAINT-BASED LOGIC CELL PLACEMENT
    1.
    发明申请
    FLEXIBLE CONSTRAINT-BASED LOGIC CELL PLACEMENT 有权

    公开(公告)号：US20210064716A1

    公开(公告)日：2021-03-04

    申请号：US16559976

    申请日：2019-09-04

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： David WOLPERT ,  Timothy A. SCHELL ,  Erwin BEHNEN ,  Leon SIGAL

    IPC: G06F17/50

    Abstract: Methods, systems and computer program products for providing flexible constraint-based logic cell placement are provided. Aspects include determining a cell placement restriction rule that specifies an offset requirement between a first type of logic cell and a second type of logic cell. Responsive to placing a first cell that is the first type of logic cell within a semiconductor layout, aspects include tagging the first cell with the cell placement restriction rule. Aspects also include placing a second cell that is the second type of logic cell at an initial position within the semiconductor layout. Responsive to determining that the initial position of the second cell violates the cell placement restriction rule, aspects include repositioning the first cell or the second cell to a modified position within the semiconductor layout such that the modified position satisfies the cell placement restriction rule.

    IDENTIFYING EXCESS ANTENNAS WITHIN INTEGRATED CIRCUIT DESIGNS
    2.
    发明申请
    IDENTIFYING EXCESS ANTENNAS WITHIN INTEGRATED CIRCUIT DESIGNS 有权

    公开(公告)号：US20250131171A1

    公开(公告)日：2025-04-24

    申请号：US18491575

    申请日：2023-10-20

    Applicant: International Business Machines Corporation

    Inventor： Amanda Christine VENTON ,  Eric Chien LAI ,  David WOLPERT ,  Michael Alexander BOWEN ,  Miles C. PEDRONE

    IPC: G06F30/323 ,  G06F30/31 ,  G06F30/392

    Abstract: Embodiments herein describe techniques for identifying excess antennas (or antenna diodes) in a IC design using computer software tools. An IC design can be changed for any number of reasons, which can change the number of antennas that are required to sufficiently protect the IC from damage during the fabrication process. Currently, a chip designer would use a ratio to determine whether a portion of the IC (e.g., a macro) has too many or too few antennas. The embodiments herein describe techniques where computer software tools identify excess antennas for the designer. The designer can then decide whether to remove these antennas. In another embodiment, the computer software tools may automatically remove some or all of the identified excess antennas, without input from the chip designer.

    DEFINED CIRCUIT STRUCTURE PATTERN IDENTIFICATION AND PLACEMENT AVOIDANCE
    3.
    发明申请
    DEFINED CIRCUIT STRUCTURE PATTERN IDENTIFICATION AND PLACEMENT AVOIDANCE 有权

    公开(公告)号：US20250021734A1

    公开(公告)日：2025-01-16

    申请号：US18349390

    申请日：2023-07-10

    Applicant: International Business Machines Corporation

    Inventor： Richard Edward SERTON ,  David WOLPERT ,  Michael Alexander BOWEN ,  Henry A. BONGES, III

    IPC: G06F30/392

    Abstract: Embodiments of the present disclosure provide systems and methods for implementing defined circuit structure pattern identification and placement avoidance in an integrated circuit. Disclosed embodiments identify regions of circuits containing potentially problematic content from review of physical design data of at least a portion of the integrated circuit. The identified circuits containing problematic content along at least one circuit boundary are marked with a keyword. The keyword is maintained with the identified problematic circuit throughout the hierarchical construction of the integrated circuit. The keyword is used to keep the identified problematic circuits spaced apart from other sensitive circuits to avoid performance disruption of adjacent sensitive circuits.

    SEMICONDUCTOR DEVICE DESIGN MITIGATING LATCH-UP
    4.
    发明公开
    SEMICONDUCTOR DEVICE DESIGN MITIGATING LATCH-UP 审中-公开

    公开(公告)号：US20230307363A1

    公开(公告)日：2023-09-28

    申请号：US17656368

    申请日：2022-03-24

    Applicant: International Business Machines Corporation

    Inventor： David WOLPERT ,  Leon SIGAL ,  Terence HOOK

    IPC: H01L23/528 ,  H01L27/092

    CPC classification number: H01L23/5286 ,  H01L27/092

    Abstract: Apparatus for mitigating latch-up within semiconductor devices. A semiconductor device includes a first conductor, a second conductor, and a first gate conductor. The first conductor extends in a first direction, receives a first power supply signal, and is connected to a first electrode. The second conductor extends in the first direction, receives a second power supply signal different from the first power supply signal, and is connected to a second electrode. The first conductor is offset from the second conductor in a second direction perpendicular to the first direction in a top-down view to mitigate formation of parasitic devices within the semiconductor device electrically connecting the first conductor with the second conductor. The first gate conductor is disposed adjacent to the first conductor and the second conductor, is disposed on the first electrode and the second electrode, and receives an input signal.

    CELL OPTIMIZATION THROUGH SOURCE RESISTANCE IMPROVEMENT
    5.
    发明公开
    CELL OPTIMIZATION THROUGH SOURCE RESISTANCE IMPROVEMENT 审中-公开

    公开(公告)号：US20230317610A1

    公开(公告)日：2023-10-05

    申请号：US17657304

    申请日：2022-03-30

    Applicant: International Business Machines Corporation

    Inventor： David WOLPERT ,  Leon SIGAL ,  Bharat BIYANI

    IPC: H01L23/528 ,  G06F30/392

    CPC classification number: H01L23/5286 ,  H01L23/5226 ,  G06F30/392

    Abstract: Method and structures for shared (dual) sources for a single device in semiconductor devices such as very-large-scale integration (VLSI) devices. The shared-source improves or increases a current that passes through the device (e.g., to a drain region associated with the shared-source), which in turn increases a performance of the device. Example improvements may include a delay improvement of the device and associated logic paths and/or a power improvement for the device. The method includes operations for design improvements during a design process by implementing shared-sources in a semiconductor device design.

    FILL TECHNIQUES FOR AVOIDING BOOLEAN DRC FAILURES DURING CELL PLACEMENT
    8.
    发明申请
    FILL TECHNIQUES FOR AVOIDING BOOLEAN DRC FAILURES DURING CELL PLACEMENT 有权

    公开(公告)号：US20210064719A1

    公开(公告)日：2021-03-04

    申请号：US16559967

    申请日：2019-09-04

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： David WOLPERT ,  Timothy A. SCHELL ,  Michael GRAY ,  Erwin BEHNEN ,  Robert Mahlon AVERILL, III

    IPC: G06F17/50

    Abstract: Methods, systems and computer program products for avoiding Boolean DRC failures during cell placement are provided. Aspects include generating a semiconductor layout by filling a plurality of rows within a macro block with cells including functional cells and fill cells. Aspects also include modifying the semiconductor layout by removing one or more fill cells from the macro block to create a gap. Aspects also include examining a set of cells that border edges of the gap to identify one or more predicted rule violations. Based on the identified one or more predicted rule violations, aspects also include modifying the semiconductor layout to change a shape of the gap to avoid the one or more predicted rule violations.

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