公开(公告)号：US20190215282A1

公开(公告)日：2019-07-11

申请号：US15865530

申请日：2018-01-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. BRIGGS ,  Lawrence A. CLEVENGER ,  Leigh Anne H. CLEVENGER ,  Christoper J. PENNY ,  Michael RIZZOLO ,  Aldis SIPOLINS

IPC: H04L12/58 ,  G06F17/27 ,  G06F15/18 ,  H04L29/08

Abstract: Context appropriate errors are injected into conversational text generated by conversational agents. The conversational agent creates an imperfect conversational text containing at least one text entry error added to the original conversational text. A confidence level that at least one of context and meaning of the imperfect conversational text is consistent with the context and meaning of the original conversational text is determined, and the imperfect conversational text is communicated to a human recipient if the confidence level is above a pre-defined threshold.

公开(公告)号：US20180368757A1

公开(公告)日：2018-12-27

申请号：US15801720

申请日：2017-11-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mahmoud AMIN ,  Zhenxing BI ,  Lawrence A. CLEVENGER ,  Leigh Anne H. CLEVENGER ,  Krishna R. TUNGA

IPC: A61B5/00 ,  G16H50/20 ,  G16H20/30 ,  G16H15/00

CPC classification number: A61B5/4815 ,  A61B5/00 ,  A61B5/0022 ,  A61B5/1118 ,  A61B5/1123 ,  A61B5/68 ,  A61B5/681 ,  A61B5/6898 ,  G16B20/20 ,  G16H10/60 ,  G16H15/00 ,  G16H20/30 ,  G16H40/63 ,  G16H40/67 ,  G16H50/20 ,  G16H50/30

Abstract: Embodiments of the invention are directed to a computer-implemented method for generating a sleep optimization plan. A non-limiting example of the computer-implemented method includes receiving, by a processor, genetic data for a user. The method also includes receiving, by the processor, Internet of Things (IoT) device data for the user. The method also includes generating, by the processor, a sleep duration measurement for the user based at last in part upon the IoT device data. The method also includes generating, by the processor, a sleep optimization plan for the user based at least in part upon the genetic data.

公开(公告)号：US20180254242A1

公开(公告)日：2018-09-06

申请号：US15966236

申请日：2018-04-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. BRIGGS ,  Lawrence A. CLEVENGER ,  Bartlet H. DeProspo ,  Michael RIZZOLO ,  Nicole A. SAULNIER

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53228

Abstract: A method of forming a self-aligned pattern of vias in a semiconductor device comprises etching a pattern of lines that contain notches that are narrower than other parts of the line. Thereafter, vias are created where the notches are located. The locations of the vias are such that the effect of blown-out areas is minimized. Thereafter, the lines are etched and the vias and line areas are filled. The layers are planarized such that the metal fill is level with a surrounding ultra-low-k dielectric. Additional metal layers, lines, and vias can be created. Other embodiments are also described herein.

公开(公告)号：US20190326289A1

公开(公告)日：2019-10-24

申请号：US16460018

申请日：2019-07-02

Applicant: International Business Machines Corporation

Inventor： Lawrence A. CLEVENGER ,  Leigh Anne H. CLEVENGER ,  Mona A. EBRISH ,  Gauri KARVE ,  Fee Li LIE ,  Deepika PRIYADARSHINI ,  Indira Priyavarshini SESHADRI ,  Nicole A. SAULNIER

IPC: H01L27/092 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/161 ,  H01L29/06 ,  H01L29/66 ,  H01L21/308 ,  H01L29/10

Abstract: A method for fabricating fin field effect transistors comprises creating a pattern of self-aligned small cavities for P-type material growth using at least two hard mask layers, generating a pre-defined isolation area around each small cavity using a vertical spacer, selectively removing N-type material from the self-aligned small cavities, and growing P-type material in the small cavities. The P-type material may be silicon germanium (SiGe) and the N-type material may be tensile Silicon (t-Si). The pattern of self-aligned small cavities for P-type material growth is created by depositing two hard mask materials over a starting substrate wafer, selectively depositing photo resist over a plurality N-type areas, reactive ion etching to remove the second hard mask layer material over areas not covered by photo resist to create gaps in second hard mask layer, and removing the photo resist to expose the second hard mask material in the N-type areas.

公开(公告)号：US20190262941A1

公开(公告)日：2019-08-29

申请号：US16410475

申请日：2019-05-13

Applicant: International Business Machines Corporation

Inventor： Benjamin David BRIGGS ,  Lawrence A. CLEVENGER ,  Bartle H. DEPROSPO ,  Michael RIZZOLO

IPC: B23K26/082 ,  H01L21/66 ,  H01L21/768 ,  B23K26/352 ,  B23K26/062 ,  B23K26/03 ,  B23K26/00 ,  H01L21/67 ,  B23K26/70

Abstract: A method (and structure) includes performing an initial partial anneal of a metal interconnect overburden layer for semiconductor devices being fabricated on a chip on a semiconductor wafer. Orientation of an early recrystallizing grain at a specific location on a top surface of the metal overburden layer is determined, as implemented and controlled by a processor on a computer. A determination is made whether the orientation of the early recrystallizing grain is desirable or undesirable.

公开(公告)号：US20180366141A1

公开(公告)日：2018-12-20

申请号：US15622577

申请日：2017-06-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Maryam ASHOORI ,  Benjamin D. BRIGGS ,  Lawrence A. CLEVENGER ,  Leigh Anne H. CLEVENGER ,  Michael RIZZOLO

IPC: G10L25/63 ,  G06F19/00 ,  G10L15/26 ,  A61B5/16

Abstract: Embodiments of the present invention are directed to a computer program product for generating a personality shift determination. The computer program product can include a computer readable storage medium having program instructions embodied therewith, wherein the instructions are executable by a processor to cause the processor to perform a method. The method can include receiving a real-time audio input. The method can also include generating a real-time personality trait identification. The method can also include generating a current trait classification for the real-time personality trait identification. The method can also include comparing the current trait classification to a historic rate classification. The method can also include generating a personality shift determination.

公开(公告)号：US20160190312A1

公开(公告)日：2016-06-30

申请号：US14588337

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John H. ZHANG ,  Carl RADENS ,  Lawrence A. CLEVENGER ,  Yiheng XU

IPC: H01L29/78 ,  H01L29/16 ,  H01L21/28 ,  H01L29/267 ,  H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L29/165

CPC classification number: H01L29/7827 ,  H01L21/823871 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/165 ,  H01L29/66666

Abstract: Vertical GAA FET structures are disclosed in which a current-carrying nanowire is oriented substantially perpendicular to the surface of a silicon substrate. The vertical GAA FET is intended to meet design and performance criteria for the 7 nm technology generation. In some embodiments, electrical contacts to the drain and gate terminals of the vertically oriented GAA FET can be made via the backside of the substrate. Examples are disclosed in which various n-type and p-type transistor designs have different contact configurations. In one example, a backside gate contact extends through the isolation region between adjacent devices. Other embodiments feature dual gate contacts for circuit design flexibility. The different contact configurations can be used to adjust metal pattern density.

Abstract translation: 公开了垂直GAA FET结构，其中载流纳米线基本上垂直于硅衬底的表面取向。 垂直GAA FET旨在满足7 nm技术生成的设计和性能标准。 在一些实施例中，可以经由衬底的背面制造垂直取向的GAA FET的漏极和栅极端子的电接触。 公开了各种n型和p型晶体管设计具有不同接触构造的实例。 在一个示例中，背面栅极触点延伸穿过相邻器件之间的隔离区域。 其他实施例具有用于电路设计灵活性的双栅极触点。 可以使用不同的接触配置来调整金属图案密度。

公开(公告)号：US20200027840A1

公开(公告)日：2020-01-23

申请号：US16039570

申请日：2018-07-19

Applicant: International Business Machines Corporation

Inventor： Benjamin D. BRIGGS ,  Cornelius Brown PEETHALA ,  Michael RIZZOLO ,  Koichi MOTOYAMA ,  Gen TSUTSUI ,  Ruqiang BAO ,  Gangadhara Raja MUTHINTI ,  Lawrence A. CLEVENGER

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L21/306 ,  H01L21/48

Abstract: A method for fabricating semiconductor wafers comprises creating a semiconductor wafer having a plurality of wide copper wires and a plurality of narrow copper wires embedded in a dielectric insulator. The width of each wide copper wire is greater than a cutoff value and each narrow copper is less than the cutoff value. An optical pass through layer is deposited over a top surface of the wafer and a photo-resist layer is deposited over the optical pass through layer. The wafer is exposed to a light source to selectively remove photo-resist, forming a self-aligned pattern where photo-resist only remains in areas above wide copper wires. The self-aligned pattern is transferred to the optical pass through layer and the remaining photo-resist is removed. The wafer is chemically etched to remove the narrow copper wires, defining narrow gaps in the dielectric insulator. The wafer is metallized with non-copper metal, forming narrow non-copper metal wires.

公开(公告)号：US20190340324A1

公开(公告)日：2019-11-07

申请号：US15969841

申请日：2018-05-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： David WOLPERT ,  Erwin BEHNEN ,  Lawrence A. CLEVENGER ,  Patrick WATSON ,  Chih-Chao YANG ,  Timothy A. SCHELL

IPC: G06F17/50 ,  H01L27/02

Abstract: A technique relates to structuring a semiconductor device. First empty cells are placed against hierarchical boundaries of a macro block. Functional cells are added in the macro block. Remaining areas are filled with second empty cells in the macro block. Shape requirements are determined for the first empty cells and the second empty cells. The first and second empty cells are replaced with determined shape requirements.

公开(公告)号：US20180366408A1

公开(公告)日：2018-12-20

申请号：US16049442

申请日：2018-07-30

Applicant: International Business Machines Corporation

Inventor： Benjamin David BRIGGS ,  Lawrence A. CLEVENGER ,  Bartlef H. DEPROSPO ,  Huai HUANG ,  Christopher J. PENNY ,  Michael RIZZOLO

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53219 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329 ,  H01L2221/1047

Abstract: A method of forming a semiconductor device includes forming a porous dielectric layer including a recessed portion, forming a conductive layer in the recessed portion of the porous dielectric layer, and forming a conformal cap layer on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the conformal cap layer.