公开(公告)号：US20180336037A1

公开(公告)日：2018-11-22

申请号：US15597394

申请日：2017-05-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brian D. BARRICK ,  Steven J. BATTLE ,  Joshua W. BOWMAN ,  Hung Q. LE ,  Dung Q. NGUYEN ,  David R. TERRY ,  Albert J. VAN NORSTRAND, JR.

IPC: G06F9/38 ,  G06F9/30

Abstract: Embodiments include systems, methods, and computer program products for using a multi-level history buffer (HB) for a speculative transaction. One method includes after dispatching a first instruction indicating start of the speculative transaction, marking one or more register file (RF) entries as pre-transaction memory (PTM), and after dispatching a second instruction targeting one of the marked RF entries, moving data from the marked RF entry to a first level HB entry and marking the first level HB entry as PTM. The method also includes upon detecting a write back to the first level HB entry, moving data from the first level HB entry to a second level HB entry and marking the second level HB entry as PTM. The method further includes upon determining that the second level HB entry has been completed, moving data from the second level HB entry to a third level HB entry.

公开(公告)号：US20200301758A1

公开(公告)日：2020-09-24

申请号：US16360920

申请日：2019-03-21

Applicant: International Business Machines Corporation

Inventor： Steven J. BATTLE ,  Dung Q. NGUYEN ,  Hung Q. LE ,  James W. BISHOP ,  Brian W. THOMPTO ,  Susan E. EISEN

IPC: G06F9/52 ,  G06F9/46 ,  G06F9/48

Abstract: A processor configured to manage a transaction memory (TM) state. The processor is configured to receive a first instruction indicating a start of a speculative transaction and update a register file with a speculative transaction memory (TM) state corresponding to the speculative transaction. The processor is further configured to determine whether or not the register file is able to store the entirety of speculative TM state. If the register file is unable to store the entirety of the speculative TM state, the processor is configured to copy a previous TM (pre-TM) state from the register file to a memory which is external to the processor. Further, the processor may be configured to complete updating the register file with the speculative TM state after the pre-TM state has been copied from the register file to the memory.

公开(公告)号：US20170109167A1

公开(公告)日：2017-04-20

申请号：US14883301

申请日：2015-10-14

Applicant: International Business Machines Corporation

Inventor： Susan E. EISEN ,  Cliff KUCHARSKI ,  Hung Q. LE ,  Dung Q. NGUYEN ,  David R. TERRY

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/30072 ,  G06F9/30 ,  G06F9/30098 ,  G06F9/3857 ,  G06F9/3861 ,  G06F12/0875 ,  G06F12/0891 ,  G06F2212/60

Abstract: Method and system for restoring data to a register file of a processing unit are provided. A history buffer entry (HBE) is marked for restoration to a register file entry. Result data and control information is sent from the HBE to an Issue Queue (ISQ). The ISQ issues an instruction for loading the result data into the register file entry based on the control information. A write back operation is performed to restore the result data to the register file entry, in response to issuing of the instruction.

公开(公告)号：US20170109171A1

公开(公告)日：2017-04-20

申请号：US14883349

申请日：2015-10-14

Applicant: International Business Machines Corporation

Inventor： Susan E. EISEN ,  Cliff KUCHARSKI ,  Hung Q. LE ,  Dung Q. NGUYEN ,  David R. TERRY

IPC: G06F9/38 ,  G06F12/08 ,  G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/30098 ,  G06F9/3857 ,  G06F9/3885 ,  G06F9/3887 ,  G06F12/0875 ,  G06F12/0891 ,  G06F2212/60

Abstract: Method and system for writing a history buffer in a processing unit is provided. At least a first instruction and a second instruction are dispatched in a single processing cycle, targeting a same register file entry. The processing unit includes two or more processing slices, each processing slice comprising a corresponding history buffer and at least a portion of a register file. Upon determining that first result data corresponding to the first instruction is older than second result data corresponding to the second instruction, the first result data is written into a history buffer bypassing the register file entry, in response to the determination. Further, the second result data is written into the register file entry.

公开(公告)号：US20170109166A1

公开(公告)日：2017-04-20

申请号：US14883253

申请日：2015-10-14

Applicant: International Business Machines Corporation

Inventor： Susan E. EISEN ,  Cliff KUCHARSKI ,  Hung Q. LE ,  Dung Q. NGUYEN ,  David R. TERRY

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/30072 ,  G06F9/30 ,  G06F9/30098 ,  G06F9/3857 ,  G06F9/3861 ,  G06F12/0875 ,  G06F12/0891 ,  G06F2212/452

Abstract: Method and system for restoring results to a register file of a processing unit is provided. An instruction is dispatched in a processing slice of the processing unit, targeting a register file, wherein the processing unit includes two or more processing slices, each processing slice including a corresponding history buffer and at least a portion of a register file. The processing unit evicts previous result data from the register file entry to a history buffer corresponding to the processing slice, by writing new result data into the register file entry, in response to the instruction. The processing unit detects a trigger condition relating to a rollback of the processing unit to a previous state, and restores the previous result data from the history buffer to the register file entry, in response to the trigger.