公开(公告)号：US20170308454A1

公开(公告)日：2017-10-26

申请号：US15138593

申请日：2016-04-26

Applicant: International Business Machines Corporation

Inventor： Khandker N. ADEEB ,  Steven J. BATTLE ,  Brandon R. GODDARD ,  Dung Q. NGUYEN ,  Tu-An T. NGUYEN ,  Nicholas R. ORZOL ,  Brian D. VICTOR ,  Brendan M. WONG

IPC: G06F11/34 ,  G06F11/30

CPC classification number: G06F11/3495 ,  G01R31/31705 ,  G06F11/3024

Abstract: Systems, methods, and apparatuses to perform an operation comprising receiving an indication of a first error in a processor, identifying a first control signal, of a plurality of control signals in a debug bus, associated with the error, wherein each of the plurality of control signals are coupled to one of a plurality of input ports of a multiplexer, and changing a configuration state of the multiplexer to output the first control signal to a trace array.

公开(公告)号：US20180336037A1

公开(公告)日：2018-11-22

申请号：US15597394

申请日：2017-05-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brian D. BARRICK ,  Steven J. BATTLE ,  Joshua W. BOWMAN ,  Hung Q. LE ,  Dung Q. NGUYEN ,  David R. TERRY ,  Albert J. VAN NORSTRAND, JR.

IPC: G06F9/38 ,  G06F9/30

Abstract: Embodiments include systems, methods, and computer program products for using a multi-level history buffer (HB) for a speculative transaction. One method includes after dispatching a first instruction indicating start of the speculative transaction, marking one or more register file (RF) entries as pre-transaction memory (PTM), and after dispatching a second instruction targeting one of the marked RF entries, moving data from the marked RF entry to a first level HB entry and marking the first level HB entry as PTM. The method also includes upon detecting a write back to the first level HB entry, moving data from the first level HB entry to a second level HB entry and marking the second level HB entry as PTM. The method further includes upon determining that the second level HB entry has been completed, moving data from the second level HB entry to a third level HB entry.

公开(公告)号：US20190187995A1

公开(公告)日：2019-06-20

申请号：US15844998

申请日：2017-12-18

Applicant: International Business Machines Corporation

Inventor： David R. TERRY ,  Dung Q. NGUYEN ,  Brian W. THOMPTO ,  Joshua W. BOWMAN ,  Steven J. BATTLE ,  Brian D. BARRICK ,  Sundeep CHADHA ,  Albert J. VAN NORSTRAND, JR.

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3859 ,  G06F9/30105 ,  G06F9/30127 ,  G06F9/30145 ,  G06F9/3806 ,  G06F9/3844 ,  G06F9/3851

Abstract: Techniques are disclosed for performing a flush and restore of a history buffer (HB) in a processing unit. One technique inludes identifying one or more entries of the HB to restore to a register file in the processing unit. For each of the one or more HB entries, a determination is made whether to send the HB entry to the register file via a first restore bus or via a second restore bus, different from the first restore bus, based on contents of the HB entry. Each of the one or more HB entries is then sent to the register file via one of the first restore bus or the second restore bus, based on the determination.

公开(公告)号：US20190171569A1

公开(公告)日：2019-06-06

申请号：US15831658

申请日：2017-12-05

Applicant: International Business Machines Corporation

Inventor： Steven J. BATTLE ,  Dung Q. Nguyen ,  Susan E. Eisen ,  Kenneth L. Ward ,  Eula Faye Abalos Tolentino ,  Cliff Kucharski ,  Glenn O. Kincaid ,  David S. Walder

IPC: G06F12/0855 ,  G06F12/0877 ,  G06F12/0895 ,  G06F12/0897

Abstract: Embodiments include systems, methods, and computer program products for using a multi-tier hang buster for detecting and breaking out of hang conditions in a processor. One method includes determining a plurality of actions available at each of a plurality of tiers used for breaking out of the hang condition in the processor. The method also includes, after detecting the hang condition on a first thread of the processor, performing one or more actions available at a first tier of the plurality of tiers to break out of the hang condition. The method further includes, after performing the one or more actions at the first tier and determining that the hang condition is still present, performing one or more actions available at one or more second tiers of the plurality of tiers to break out of the hang condition.

公开(公告)号：US20200301758A1

公开(公告)日：2020-09-24

申请号：US16360920

申请日：2019-03-21

Applicant: International Business Machines Corporation

Inventor： Steven J. BATTLE ,  Dung Q. NGUYEN ,  Hung Q. LE ,  James W. BISHOP ,  Brian W. THOMPTO ,  Susan E. EISEN

IPC: G06F9/52 ,  G06F9/46 ,  G06F9/48

Abstract: A processor configured to manage a transaction memory (TM) state. The processor is configured to receive a first instruction indicating a start of a speculative transaction and update a register file with a speculative transaction memory (TM) state corresponding to the speculative transaction. The processor is further configured to determine whether or not the register file is able to store the entirety of speculative TM state. If the register file is unable to store the entirety of the speculative TM state, the processor is configured to copy a previous TM (pre-TM) state from the register file to a memory which is external to the processor. Further, the processor may be configured to complete updating the register file with the speculative TM state after the pre-TM state has been copied from the register file to the memory.

公开(公告)号：US20190188133A1

公开(公告)日：2019-06-20

申请号：US15845757

申请日：2017-12-18

Applicant: International Business Machines Corporation

Inventor： David R. TERRY ,  Dung Q. NGUYEN ,  Brian W. THOMPTO ,  Joshua W. BOWMAN ,  Steven J. BATTLE ,  Sundeep CHADHA ,  Brian D. BARRICK ,  Albert J. VAN NORSTRAND, JR.

IPC: G06F12/0804

CPC classification number: G06F12/0804 ,  G06F2212/1008 ,  G06F2212/1016

Abstract: Techniques are disclosed for performing issue queue snooping for an asynchronous flush and restore of a history buffer (HB) in a processing unit. One technique includes identifying an entry of the HB to restore to a register file in the processing unit. A restore ITAG of the HB entry is sent to the register file via a first restore bus, and restore data of the HB entry and the restore ITAG is sent to the register file via a second restore bus. After the restore ITAG and restore data are sent, an instruction is dispatched before the register file obtains the restore data. After it is determined that the restore data is still available via the second restore bus, a snooping operation is performed to obtain the restore data from the second restore bus for the dispatched instruction.

公开(公告)号：US20180336108A1

公开(公告)日：2018-11-22

申请号：US15596818

申请日：2017-05-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Steven J. BATTLE ,  Joshua W. BOWMAN ,  Sundeep CHADHA ,  Dhivya JEGANATHAN ,  Cliff KUCHARSKI ,  Dung Q. NGUYEN ,  Tu-An T. NGUYEN ,  David R. TERRY

IPC: G06F11/16 ,  G06F11/20 ,  G06F9/30 ,  G06F9/38

Abstract: Embodiments include systems, methods, and computer program products for on-demand error detection and correction of registers in a processor. One method includes detecting, before a first instruction is dispatched to an issue queue in the processor, an error in data, associated with the first instruction, stored in an entry of a register file in the processor. The method also includes, after detecting the error, halting the dispatch of the first instruction to the issue queue, and determining whether the entry of the register file has completed. The method further includes determining whether to perform error correction on the register file based on the determination of whether the entry of the register file has completed.

公开(公告)号：US20170344380A1

公开(公告)日：2017-11-30

申请号：US15163314

申请日：2016-05-24

Applicant: International Business Machines Corporation

Inventor： Brian D. BARRICK ,  Steven J. BATTLE ,  Joshua W. BOWMAN ,  Christopher M. MUELLER ,  Dung Q. NGUYEN ,  David R. TERRY ,  Eula Faye TOLENTINO ,  Jing ZHANG

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3863 ,  G06F9/3857

Abstract: Techniques are disclosed for restoring register data in a processor. In one embodiment, a method includes receiving an instruction to flush one or more general purpose registers (GPRs) in a processor. The method also includes determining history buffer entries of a history buffer to be restored to the one or more GPRs. The method includes creating a mask vector that indicates which history buffer entries will be restored to the one or more GPRs. The method further includes restoring the indicated history buffer entries to the one or more GPRs. As each indicated history buffer entry is restored, the method includes updating the mask vector to indicate which history buffer entries have been restored.