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    PARTIAL ECC MECHANISM FOR A BYTE-WRITE CAPABLE REGISTER
    1.
    发明申请
    PARTIAL ECC MECHANISM FOR A BYTE-WRITE CAPABLE REGISTER 审中-公开
    用于字节写能力寄存器的部分ECC机制

    公开(公告)号：US20170063401A1

    公开(公告)日：2017-03-02

    申请号：US14842488

    申请日：2015-09-01

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Dhivya JEGANATHAN ,  Dung Q. NGUYEN ,  Jose A. PAREDES ,  David R. TERRY ,  Brian W. THOMPTO

    IPC: H03M13/29 ,  G11C29/52 ,  G06F11/10

    CPC classification number: G06F11/1004 ,  G06F11/1048 ,  G06F11/1076 ,  H03M13/13 ,  H03M13/2909 ,  H03M13/3761

    Abstract: Embodiments described herein include a computing system that permits partial writes into a memory element—e.g., a register on a processor. For example, the data to be written into the memory element may be spread across multiple sources. The register may receive data from two different sources at different times and perform two separate partial write commands to store the data. Embodiments herein generate an ECC value for each of the partial writes. That is, when storing the data of the first partial write, the computing system generates a first ECC value for the data in the first partial write and stores this value in the memory element. Later, when performing the second partial write, the computing system generates a second ECC value for this data which is also stored in the memory element.

    Abstract translation: 本文描述的实施例包括允许部分写入存储器元件的计算系统，例如处理器上的寄存器。 例如，要写入存储元件的数据可以分布在多个源上。 寄存器可以在不同时间从两个不同的源接收数据，并执行两个单独的部分写入命令来存储数据。 本文的实施例为每个部分写入生成ECC值。 也就是说，当存储第一部分写入的数据时，计算系统为第一部分写入中的数据生成第一ECC值，并将该值存储在存储器元件中。 之后，当执行第二部分写入时，计算系统生成也存储在存储元件中的该数据的第二ECC值。

    MULTI-LEVEL HISTORY BUFFER FOR TRANSACTION MEMORY IN A MICROPROCESSOR
    3.
    发明申请
    MULTI-LEVEL HISTORY BUFFER FOR TRANSACTION MEMORY IN A MICROPROCESSOR 审中-公开

    公开(公告)号：US20180336037A1

    公开(公告)日：2018-11-22

    申请号：US15597394

    申请日：2017-05-17

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Brian D. BARRICK ,  Steven J. BATTLE ,  Joshua W. BOWMAN ,  Hung Q. LE ,  Dung Q. NGUYEN ,  David R. TERRY ,  Albert J. VAN NORSTRAND, JR.

    IPC: G06F9/38 ,  G06F9/30

    Abstract: Embodiments include systems, methods, and computer program products for using a multi-level history buffer (HB) for a speculative transaction. One method includes after dispatching a first instruction indicating start of the speculative transaction, marking one or more register file (RF) entries as pre-transaction memory (PTM), and after dispatching a second instruction targeting one of the marked RF entries, moving data from the marked RF entry to a first level HB entry and marking the first level HB entry as PTM. The method also includes upon detecting a write back to the first level HB entry, moving data from the first level HB entry to a second level HB entry and marking the second level HB entry as PTM. The method further includes upon determining that the second level HB entry has been completed, moving data from the second level HB entry to a third level HB entry.

    PARTIAL ECC HANDLING FOR A BYTE-WRITE CAPABLE REGISTER
    4.
    发明申请
    PARTIAL ECC HANDLING FOR A BYTE-WRITE CAPABLE REGISTER 有权
    用于字节写入寄存器的部分ECC处理

    公开(公告)号：US20170060678A1

    公开(公告)日：2017-03-02

    申请号：US14842521

    申请日：2015-09-01

    Applicant: International Business Machines Corporation

    Inventor： Dhivya JEGANATHAN ,  Dung Q. NGUYEN ,  Jose A. PAREDES ,  David R. TERRY ,  Brian W. THOMPTO

    IPC: G06F11/10 ,  G11C29/52

    CPC classification number: G06F11/1068 ,  G06F11/1056 ,  G11C29/52 ,  G11C2029/0411

    Abstract: Embodiments described herein include a computing system that permits partial writes into a memory element—e.g., a register on a processor. For example, the data to be written into the memory element may be spread across multiple sources. The register may receive data from two different sources at different times and perform two separate partial write commands to store the data. Embodiments herein generate an ECC value for each of the partial writes. That is, when storing the data of the first partial write, the computing system generates a first ECC value for the data in the first partial write and stores this value in the memory element. Later, when performing the second partial write, the computing system generates a second ECC value for this data which is also stored in the memory element.

    Abstract translation: 本文描述的实施例包括允许部分写入存储器元件的计算系统，例如处理器上的寄存器。 例如，要写入存储元件的数据可以分布在多个源上。 寄存器可以在不同时间从两个不同的源接收数据，并执行两个单独的部分写入命令来存储数据。 本文的实施例为每个部分写入生成ECC值。 也就是说，当存储第一部分写入的数据时，计算系统为第一部分写入中的数据生成第一ECC值，并将该值存储在存储元件中。 之后，当执行第二部分写入时，计算系统生成也存储在存储元件中的该数据的第二ECC值。

    GENERATING ECC VALUES FOR BYTE-WRITE CAPABLE REGISTERS
    6.
    发明申请
    GENERATING ECC VALUES FOR BYTE-WRITE CAPABLE REGISTERS 有权
    生成用于字节写入寄存器的ECC值

    公开(公告)号：US20170060677A1

    公开(公告)日：2017-03-02

    申请号：US14868544

    申请日：2015-09-29

    Applicant: International Business Machines Corporation

    Inventor： Dhivya JEGANATHAN ,  Dung Q. NGUYEN ,  Jose A. PAREDES ,  David R. TERRY ,  Brian W. THOMPTO

    IPC: G06F11/10 ,  H03M13/29

    CPC classification number: H03M13/2906 ,  G06F11/1056 ,  G06F11/1064 ,  G11C2029/0411

    Abstract: Embodiments described herein include a computing system that permits partial writes into a memory element—e.g., a register on a processor. For example, the data to be written into the memory element may be spread across multiple sources. The register may receive data from two different sources at different times and perform two separate partial write commands to store the data. Embodiments herein generate an ECC value for each of the partial writes. That is, when storing the data of the first partial write, the computing system generates a first ECC value for the data in the first partial write and stores this value in the memory element. Later, when performing the second partial write, the computing system generates a second ECC value for this data which is also stored in the memory element.

    Abstract translation: 本文描述的实施例包括允许部分写入存储器元件的计算系统，例如处理器上的寄存器。 例如，要写入存储元件的数据可以分布在多个源上。 寄存器可以在不同时间从两个不同的源接收数据，并执行两个单独的部分写入命令来存储数据。 本文的实施例为每个部分写入生成ECC值。 也就是说，当存储第一部分写入的数据时，计算系统为第一部分写入中的数据生成第一ECC值，并将该值存储在存储元件中。 之后，当执行第二部分写入时，计算系统生成也存储在存储元件中的该数据的第二ECC值。

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