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1.发明申请Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process 有权使用凹陷通道镶嵌栅极工艺，具有低源极和漏极电阻以及最小重叠电容的全耗尽SOI MOSFET公开(公告)号：US20030211681A1
公开(公告)日：2003-11-13
申请号：US10461821
申请日：2003-06-13
发明人： Hussein I. Hanafi , Diane C. Boyd , Kevin K. Chan , Wesley Natzle , Leathen Shi
IPC分类号： H01L021/8238
CPC分类号： H01L29/78696 , H01L29/66545 , H01L29/66772 , H01L29/78612
摘要： A sub-0.05 nullm channel length fully-depleted SOI MOSFET device having low surface and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. The sub-0.05 nullm channel length fully-depleted SOI MOSFET device includes an SOI structure which contains at least an SOI layer having a channel region of a first thickness and abutting source/drain regions of a second thickness present therein, wherein the second thickness is greater than the first thickness and the source/drain regions having a salicide layer present thereon. A gate region is present also atop the SOI layer.
摘要翻译： 提供具有低表面和漏极电阻以及最小重叠电容的0.05微米通道长度全耗尽的SOI MOSFET器件及其制造方法。 子0.05通道长度全耗尽的SOI MOSFET器件包括SOI结构，其至少包含具有第一厚度的沟道区和邻接其中存在第二厚度的源极/漏极区的SOI层，其中第二厚度为 大于第一厚度，并且源/漏区具有存在于其上的自对准硅化物层。 栅极区也存在于SOI层的顶部。
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2.发明申请METHOD OF FORMING A FULLY-DEPLETED SOI (SILICON-ON-INSULATOR) MOSFET HAVING A THINNED CHANNEL REGION 失效形成具有薄膜通道区域的全绝缘SOI（绝缘体上硅）MOSFET的方法公开(公告)号：US20030162358A1
公开(公告)日：2003-08-28
申请号：US10084550
申请日：2002-02-26
发明人： Hussein I. Hanafi , Diane C. Boyd , Kevin K. Chan , Wesley Natzle , Leathen Shi
IPC分类号： H01L021/336
CPC分类号： H01L29/78696 , H01L29/66545 , H01L29/66772 , H01L29/78612
摘要： A sub-0.05 nullm channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. The sub-0.05 nullm channel length fully-depleted SOI MOSFET device includes an SOI structure which contains at least an SOI layer having a channel region of a first thickness and abutting source/drain regions of a second thickness present therein, wherein the second thickness is greater than the first thickness and the source/drain regions having a salicide layer present thereon. A gate region is present also atop the SOI layer.
摘要翻译： 提供了具有低源极和漏极电阻以及最小重叠电容的0.05微米通道长度的全耗尽SOI MOSFET器件及其制造方法。 子0.05通道长度全耗尽的SOI MOSFET器件包括SOI结构，其至少包含具有第一厚度的沟道区和邻接其中存在第二厚度的源极/漏极区的SOI层，其中第二厚度为 大于第一厚度，并且源/漏区具有存在于其上的自对准硅化物层。 栅极区也存在于SOI层的顶部。
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3.发明申请Mosfet having a variable gate oxide thickness and a variable gate work function, and a method for making the same 审中-公开具有可变栅极氧化物厚度和可变栅极功函数的Mosfet及其制造方法公开(公告)号：US20020197810A1
公开(公告)日：2002-12-26
申请号：US09886681
申请日：2001-06-21
发明人： Hussein I. Hanafi , Suk H. Ku , Meikei Ieong
IPC分类号： H01L021/3205 , H01L021/4763 , H01L021/336
CPC分类号： H01L29/66772 , H01L29/42384 , H01L29/4908 , H01L29/78621
摘要： A transistor has a gate with a variable work function and a gate oxide layer with variable thickness. The gate oxide layer has an area of reduced thickness at its center, and the gate is made from central and peripheral portions. The central portion is formed over the central (thinner) portion of the gate oxide layer, and the peripheral portions are formed over the thicker areas of the gate oxide layer. The gate, gate oxide layer, and two source/drain regions may be formed in a damascene trench for improved performance, and lightly doped drain (LDD) regions preferably extend from the source/drain regions in overlapping relationship with the peripheral portions of the gate. Additionally, a method for making an asymmetrical transistor is presented, which involves applying a gate oxide layer on a semiconductor layer in contact with a sidewall structure. A first spacer made of a gate material is formed on the structure and gate oxide layer. An LDD region is then formed in the semiconductor layer, using the first spacer as a mask for alignment purposes. This is followed by formation of a second spacer on the gate oxide layer in overlapping relationship with the LDD region. The second spacer contacts the first spacer and is made of a gate material, and thus the first and second spacers collectively form the gate of the transistor. Final processing steps are performed to finish the device.
摘要翻译： 晶体管具有可变功函数的栅极和具有可变厚度的栅氧化层。 栅极氧化物层在其中心处具有减小厚度的区域，并且栅极由中心部分和外围部分制成。 中心部分形成在栅极氧化物层的中心（较薄）部分上，并且周边部分形成在栅极氧化物层的更厚的区域上。 栅极，栅极氧化物层和两个源极/漏极区域可以形成在镶嵌沟槽中以改善性能，并且轻掺杂漏极（LDD）区域优选地从源极/漏极区域以与栅极的周边部分重叠的关系延伸 。 此外，提出了一种用于制造不对称晶体管的方法，其涉及在与侧壁结构接触的半导体层上施加栅极氧化物层。 由栅极材料制成的第一间隔物形成在结构和栅极氧化物层上。 然后在半导体层中形成LDD区域，使用第一间隔物作为掩模用于取向目的。 接着在栅极氧化层上形成与LDD区重叠的第二间隔物。 第二间隔物接触第一间隔物并且由栅极材料制成，因此第一和第二间隔物共同形成晶体管的栅极。 执行最终处理步骤来完成设备。
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公开(公告)号：US20040046207A1
公开(公告)日：2004-03-11
申请号：US10235147
申请日：2002-09-05
IPC分类号： H01L027/01 , H01L027/12 , H01L031/0392
CPC分类号： H01L29/66772 , H01L29/458 , H01L29/78621 , H01L29/78648
摘要： A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided in which an implanted back-gate is formed into a Si-containing layer of an SOI wafer. The implanted back-gate thus formed is capable of controlling the threshold voltage of a polysilicon-containing front-gate which is formed over a portion of the implanted back-gate region. The implanted back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.
摘要翻译： 提供了一种形成绝缘体上硅（SOI）金属氧化物半导体场效应晶体管（MOSFET）器件的方法，其中注入的背栅极形成为SOI晶片的含Si层。 如此形成的注入后栅极能够控制在植入的背栅区域的一部分上形成的含多晶硅的前栅的阈值电压。 在SOI MOSFET器件中，植入式背栅可用作动态阈值电压控制系统，因为它适用于电路/系统有效期间和电路/系统空闲期间。
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5.发明申请SOI wafers with 30-100 A buried oxide (box) created by wafer bonding using 30-100 A thin oxide as bonding layer 失效具有30-100A掩埋氧化物（盒）的SOI晶片，通过使用30-100A薄氧化物作为结合层的晶片接合产生公开(公告)号：US20040018699A1
公开(公告)日：2004-01-29
申请号：US10202329
申请日：2002-07-24
IPC分类号： H01L021/30
CPC分类号： H01L21/76251 , H01L21/76243
摘要： A method of fabricating a SOI wafer having a gate-quality, thin buried oxide region is provided. The wafer is fabricating by forming a substantially uniform thermal oxide on a surface of a Si-containing layer of a SOI substrate which includes a buried oxide region positioned between the Si-containing layer and a Si-containing substrate layer. Next, a cleaning process is employed to form a hydrophilic surface on the thermal oxide. A carrier wafer having a hydrophilic surface is provided and positioned near the substrate such that the hydrophilic surfaces adjoin each other. Room temperature bonding is then employed to bond the carrier wafer to the substrate. An annealing step is performed and thereafter, the Si-containing substrate of the silicon-on-insulator substrate and the buried oxide region are selectively removed to expose the Si-containing layer.
摘要翻译： 提供一种制造具有栅极质量薄的掩埋氧化物区域的SOI晶片的方法。 通过在SOI衬底的含Si层的表面上形成基本上均匀的热氧化物来制造晶片，该衬底包括位于含Si层和含Si衬底层之间的掩埋氧化物区域。 接下来，使用清洁方法在热氧化物上形成亲水性表面。 提供具有亲水表面的载体晶片并且将其定位在基板附近，使得亲水表面彼此相邻。 然后使用室温粘合将载体晶片粘合到基底上。 进行退火工序，然后选择性地除去绝缘体上硅衬底的含Si衬底和掩埋氧化物区域以暴露含Si层。
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公开(公告)号：US20040092067A1
公开(公告)日：2004-05-13
申请号：US10609815
申请日：2003-06-30
IPC分类号： H01L021/8238
CPC分类号： H01L29/785 , H01L29/66545 , H01L29/66553 , H01L29/66795
摘要： A technique for forming a sub-0.05 nullm channel length double-gated/double channel MOSFET structure having excellent short-channel characteristics as well as the double-gated/double channel MOSFET structure itself is provided herein. The inventive technique utilizes a damascene process for the fabrication of a MOSFET device with double-gate/double channel structure. The gates are present on opposite sides of a silicon film having a vertical thickness of about 80 nm or less which is present in the gate region. The silicon film serves as the vertical channel regions of the structure and connects diffusion regions that are abutting the gate region to each other. In the inventive device, the current is double that of a conventional planar MOSFET with the same physical width due to its dual channel feature.
摘要翻译： 本文提供了一种形成具有优异的短沟道特性以及双栅/双沟道MOSFET结构本身的0.05μm以下沟道长度双栅/双沟道MOSFET结构的技术。 本发明的技术利用镶嵌工艺来制造具有双栅/双通道结构的MOSFET器件。 栅极存在于存在于栅极区域中的垂直厚度为约80nm或更小的硅膜的相对侧上。 硅膜用作结构的垂直沟道区，并且将与栅极区相邻的扩散区相互连接。 在本发明的器件中，由于其双通道特征，电流是具有相同物理宽度的常规平面MOSFET的电流的两倍。
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公开(公告)号：US20020177263A1
公开(公告)日：2002-11-28
申请号：US09866023
申请日：2001-05-24
IPC分类号： H01L029/788 , H01L029/792 , H01L029/76 , H01L021/338 , H01L021/302 , H01L021/461
CPC分类号： H01L29/785 , H01L29/66545 , H01L29/66553 , H01L29/66795
摘要： A technique for forming a sub-0.05 nullm channel length double-gated/double channel MOSFET structure having excellent short-channel characteristics as well as the double-gated/double channel MOSFET structure itself is provided herein. The inventive technique utilizes a damascene process for the fabrication of a MOSFET device with double-gate/double channel structure. The gates are present on opposite sides of a silicon film having a vertical thickness of about 80 nm or less which is present in the gate region. The silicon film serves as the vertical channel regions of the structure and connects diffusion regions that are abutting the gate region to each other. In the inventive device, the current is double that of a conventional planar MOSFET with the same physical width due to its dual channel feature.
摘要翻译： 本文提供了一种形成具有优异的短沟道特性以及双栅/双沟道MOSFET结构本身的0.05μm以下沟道长度双栅/双沟道MOSFET结构的技术。 本发明的技术利用镶嵌工艺来制造具有双栅/双通道结构的MOSFET器件。 栅极存在于存在于栅极区域中的垂直厚度为约80nm或更小的硅膜的相对侧上。 硅膜用作结构的垂直沟道区，并且将与栅极区相邻的扩散区相互连接。 在本发明的器件中，由于其双通道特征，电流是具有相同物理宽度的常规平面MOSFET的电流的两倍。
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