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1.发明申请公开(公告)号：US20040235284A1
公开(公告)日：2004-11-25
申请号：US10868791
申请日：2004-06-17
IPC分类号： H01L021/4763
CPC分类号： H01L29/66772 , H01L21/76251 , H01L29/78648
摘要： A method (and resultant structure) of forming a semiconductor device, includes forming a metal-back-gate over a substrate and a metal back-gate, forming a passivation layer on the metal back-gate to prevent the metal back-gate from reacting with radical species, and providing an intermediate gluing layer between the substrate and the metal back-gate to enhance adhesion.
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2.发明申请Self-aligned silicide process for silicon sidewall source and drain contacts and structure formed thereby 失效用于硅侧壁源极和漏极触点的自对准硅化物工艺以及由此形成的结构公开(公告)号：US20040108598A1
公开(公告)日：2004-06-10
申请号：US10437930
申请日：2003-05-15
发明人： Cyril Cabral JR. , Kevin K. Chan , Guy Moshe Cohen , Kathryn Wilder Guarini , Christian Lavoie , Paul Michael Solomon , Ying Zhang
IPC分类号： H01L023/48 , H01L023/52 , H01L029/40
CPC分类号： H01L29/6653 , H01L21/28052 , H01L21/28518 , H01L29/41783 , H01L29/456 , H01L29/66507 , H01L29/66772 , H01L29/78618 , H01L29/78684 , H01L2924/0002 , H01L2924/00
摘要： A method (and structure formed thereby) of forming a metal silicide contact on a non-planar silicon containing region having controlled consumption of the silicon containing region, includes forming a blanket metal layer over the silicon containing region, forming a silicon layer over the metal layer, etching anisotropically and selectively with respect to the metal the silicon layer, reacting the metal with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.
摘要翻译： 在具有含硅区域的受控消耗的非平面含硅区域上形成金属硅化物接触的方法（以及由此形成的结构）包括在含硅区域上形成覆盖金属层，在金属上形成硅层 层，相对于金属的硅层各向异性地选择性地蚀刻，在第一温度下使金属与硅反应以形成金属硅合金，蚀刻金属层的未反应部分，在第二温度退火以形成金属合金 -Si2，并且选择性地蚀刻未反应的硅层。
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3.发明申请METHOD AND STRUCTURE FOR ULTRA-LOW CONTACT RESISTANCE CMOS FORMED BY VERTICALLY SELF-ALIGNED COSI2 ON RAISED SOURCE DRAIN SI/SIGE DEVICE 有权通过垂直自对准COSI2形成的超低接触电阻CMOS的方法和结构在增加的SOURCE漏极SI / SIGE器件上公开(公告)号：US20030219965A1
公开(公告)日：2003-11-27
申请号：US10156782
申请日：2002-05-24
发明人： Cyril Cabral JR. , Roy A. Carruthers , Kevin K. Chan , Jack O. Chu , Guy Moshe Cohen , Steven J. Koester , Christian Lavoie , Ronnen A. Roy
IPC分类号： H01L021/3205 , H01L021/4763 , H01L021/44
CPC分类号： H01L29/41783 , H01L21/28518 , H01L21/823814 , H01L21/823835 , H01L29/161 , H01L29/665 , H01L2924/0002 , H01L2924/00
摘要： A method (and structure) of forming a vertically-self-aligned silicide contact to an underlying SiGe layer, includes forming a layer of silicon of a first predetermined thickness on the SiGe layer and forming a layer of metal on the silicon layer, where the metal layer has a second predetermined thickness. A thermal annealing process at a predetermined temperature then forms a silicide of the silicon and metal, where the predetermined temperature is chosen to substantially preclude penetration of the silicide into the underlying SiGe layer.
摘要翻译： 形成垂直自对准的硅化物接触到下面的SiGe层的方法（和结构）包括在SiGe层上形成第一预定厚度的硅层，并在硅层上形成一层金属，其中 金属层具有第二预定厚度。 然后在预定温度下的热退火工艺形成硅和金属的硅化物，其中选择预定温度以基本排除硅化物渗入下面的SiGe层。
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4.发明申请Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process 有权使用凹陷通道镶嵌栅极工艺，具有低源极和漏极电阻以及最小重叠电容的全耗尽SOI MOSFET公开(公告)号：US20030211681A1
公开(公告)日：2003-11-13
申请号：US10461821
申请日：2003-06-13
发明人： Hussein I. Hanafi , Diane C. Boyd , Kevin K. Chan , Wesley Natzle , Leathen Shi
IPC分类号： H01L021/8238
CPC分类号： H01L29/78696 , H01L29/66545 , H01L29/66772 , H01L29/78612
摘要： A sub-0.05 nullm channel length fully-depleted SOI MOSFET device having low surface and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. The sub-0.05 nullm channel length fully-depleted SOI MOSFET device includes an SOI structure which contains at least an SOI layer having a channel region of a first thickness and abutting source/drain regions of a second thickness present therein, wherein the second thickness is greater than the first thickness and the source/drain regions having a salicide layer present thereon. A gate region is present also atop the SOI layer.
摘要翻译： 提供具有低表面和漏极电阻以及最小重叠电容的0.05微米通道长度全耗尽的SOI MOSFET器件及其制造方法。 子0.05通道长度全耗尽的SOI MOSFET器件包括SOI结构，其至少包含具有第一厚度的沟道区和邻接其中存在第二厚度的源极/漏极区的SOI层，其中第二厚度为 大于第一厚度，并且源/漏区具有存在于其上的自对准硅化物层。 栅极区也存在于SOI层的顶部。
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5.发明申请公开(公告)号：US20040180510A1
公开(公告)日：2004-09-16
申请号：US10386880
申请日：2003-03-12
IPC分类号： H01L021/76
CPC分类号： H01L27/1087 , H01L21/0237 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/763 , H01L29/66181
摘要： The present invention provides methods of producing trench structures having substantially void-free filler materials therein. The fillers may be grown from a liner material such as polysilicon formed along the sidewalls of the trench. Previously formed voids may be healed by exposing the voids and growing epitaxial silicon.
摘要翻译： 本发明提供了在其中制造基本上无空隙填料的沟槽结构的方法。 填料可以从诸如沿沟槽的侧壁形成的多晶硅的衬垫材料生长。 先前形成的空隙可以通过暴露空隙和生长外延硅来治愈。
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6.发明申请Method and structure for ultra-low contact resistance CMOS formed by vertically self-alligned CoSi2 on raised source drain Si/SiGe device 失效通过垂直自对准CoSi2在升高源极Si / SiGe器件上形成的超低接触电阻CMOS的方法和结构公开(公告)号：US20030219971A1
公开(公告)日：2003-11-27
申请号：US10419888
申请日：2003-04-22
发明人： Cyril Cabral JR. , Roy A. Carruthers , Kevin K. Chan , Jack O. Chu , Guy Moshe Cohen , Steven J. Koester , Christian Lavoie , Ronnen A. Roy
IPC分类号： H01L021/3205 , H01L021/4763
CPC分类号： H01L29/41783 , H01L21/28518 , H01L21/823814 , H01L21/823835 , H01L29/161 , H01L29/665 , H01L2924/0002 , H01L2924/00
摘要： A method (and structure) of forming a vertically-self-aligned silicide contact to an underlying SiGe layer, includes forming a layer of silicon of a first predetermined thickness on the SiGe layer and forming a layer of metal on the silicon layer, where the metal layer has a second predetermined thickness. A thermal annealing process at a predetermined temperature then forms a silicide of the silicon and metal, where the predetermined temperature is chosen to substantially preclude penetration of the silicide into the underlying SiGe layer.
摘要翻译： 形成垂直自对准的硅化物接触到下面的SiGe层的方法（和结构）包括在SiGe层上形成第一预定厚度的硅层，并在硅层上形成一层金属，其中 金属层具有第二预定厚度。 然后在预定温度下的热退火工艺形成硅和金属的硅化物，其中选择预定温度以基本排除硅化物渗入下面的SiGe层。
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公开(公告)号：US20030193070A1
公开(公告)日：2003-10-16
申请号：US10411727
申请日：2003-04-11
IPC分类号： H01L029/76 , H01L029/94 , H01L031/062 , H01L031/113 , H01L031/119
CPC分类号： H01L29/66772 , H01L29/4908 , H01L29/78648
摘要： A double-gate field effect transistor (DGFET) is provided using a damascene-like replacement gate processing step to create sidewall source/drain regions, oxide spacers and gate structures inside a previously formed trench. The damascene-like replacement gate processing step allows for the fabrication of a tapered transistor body region having a thicker body under the contacts which reduces access resistance.
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8.发明申请Novel method to achieve increased trench depth, independent of CD as defined by lithography 失效实现增加沟槽深度的新方法，与光刻所定义的CD无关公开(公告)号：US20030170951A1
公开(公告)日：2003-09-11
申请号：US10093789
申请日：2002-03-07
IPC分类号： H01L021/8242
CPC分类号： H01L27/1087 , H01L21/3081 , H01L21/76224 , H01L21/76895
摘要： A method of forming at least one deep trench structure having an increased trench depth is provided. The method includes providing at least one deep trench having sidewalls that extend to a common bottom wall in a surface of a substrate. Each deep trench has initial dimensions that are wider than targeted dimensions for the deep trenches. To reduce the initial dimensions to that of the targeted dimensions, an epitaxial silicon film is formed selectively or non-selectively on at least some portions of the sidewalls using a low-temperature ultra-high vacuum epitaxial silicon growth tehnique.
摘要翻译： 提供了形成具有增加的沟槽深度的至少一个深沟槽结构的方法。 该方法包括提供至少一个具有延伸到衬底表面中的公共底壁的侧壁的深沟槽。 每个深沟槽的初始尺寸比深沟槽的目标尺寸宽。 为了将初始尺寸减小到目标尺寸的尺寸，使用低温超高真空外延硅生长技术在侧壁的至少一些部分上选择性地或非选择性地形成外延硅膜。
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公开(公告)号：US20030032272A1
公开(公告)日：2003-02-13
申请号：US09928759
申请日：2001-08-13
发明人： Jack A. Mandelman , Kevin K. Chan , Bomy A. Chen , Oleg Gluschenkov , Rajarao Jammy , Victor Ku , Chung H. Lam , Nivo Rovedo
IPC分类号： H01L021/3205
CPC分类号： H01L21/823481 , H01L21/76264 , H01L21/84 , H01L27/1203
摘要： A method for forming a JOI structure which allows for reduction in both source/drain junction leakage and capacitance is provided. In the inventive method, an insulator layer is formed under the source/drain regions, but not under the channel region. The insulator layer is formed in the present invention after forming the gate stack region and recessing the semiconductor surface surrounding the gate stack region, followed by deposition of a conductive material such as polysilicon and, optionally, heavy source/drain diffusion formation.
摘要翻译： 提供了一种形成JOI结构的方法，该方法允许减少源极/漏极结漏电流和电容。 在本发明的方法中，在源极/漏极区域之下形成绝缘体层，但不在沟道区域下方。 在本发明中，在形成栅极叠层区域并使包围栅极堆叠区域的半导体表面凹陷之后形成绝缘体层，随后沉积诸如多晶硅的导电材料，以及任选的沉积源极/漏极扩散形成。
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10.发明申请Self-aligned silicide process for reduction of Si consumption in shallow junction and thin SOI electronic devices 有权用于减少浅结和薄SOI电子器件中Si消耗的自对准硅化物工艺公开(公告)号：US20020115262A1
公开(公告)日：2002-08-22
申请号：US09791024
申请日：2001-02-21
发明人： Cyril Cabral JR. , Roy Arthur Carruthers , Kevin K. Chan , Guy M. Cohen , Kathryn Wilder Guarini , James M.E. Harper , Christian Lavoie , Paul M. Solomon
IPC分类号： H01L021/76 , H01L021/44 , H01L021/469 , H01L021/31
CPC分类号： H01L21/28518
摘要： The present invention relates to a method of reducing Si consumption during a self-aligned silicide process which employs a MnullSi or MnullSinullGe alloy, where M is Co, Ni or CoNi, and a blanket layer of Si. The present invention is particularly useful in minimizing Si consumption in shallow junction and thin silicon-on-insulator (SOI) electronic devices.
摘要翻译： 本发明涉及在采用M-Si或M-Si-Ge合金的自对准硅化物工艺中减少Si消耗的方法，其中M是Co，Ni或CoNi，以及Si的覆盖层。 本发明特别可用于最大限度地减少浅结和薄绝缘体上硅（SOI）电子器件中的Si消耗。
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