公开(公告)号：US20020153551A1

公开(公告)日：2002-10-24

申请号：US09837805

申请日：2001-04-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kwong H. Wong ,  Xian J. Ning

IPC: H01L027/108 ,  H01L029/76 ,  H01L029/94 ,  H01L031/119

CPC classification number: H01L28/60 ,  H01L21/3212 ,  H01L21/76838 ,  H01L28/75

Abstract: A method for making a metal-insulator-metal capacitive structure includes depositing a copper barrier and seed layer over a support structure such as an inter-level dielectric layer, forming a dielectric over the copper barrier and seed layer, and then forming a forming a metal layer over the dielectric. The copper barrier and seed layer forms a bottom plate of a capacitor, and the metal layer forms the upper plate which is separated from the bottom plate by the dielectric. By forming the bottom plate from a copper barrier and seed layer, reduced sheet resistance and surface roughness is achieved, both of which enhance the performance of the capacitor. This performance is further enhanced by forming the capacitor to have a damascene structure. Preferably, at least one conductive interconnect is formed simultaneously with the formation of the capacitor. This is made possible, at least in part, by forming the interconnect using a plate-through mask technique. The interconnect and capacitor are then finished using one and only one planarizing (e.g., CMP) step. The result is to form a capacitor and interconnect structure in far fewer steps than conventionally required, which translates into improved cost and efficiency.

Abstract translation: 制造金属 - 绝缘体 - 金属电容结构的方法包括在诸如层间电介质层的支撑结构上沉积铜屏障和种子层，在铜屏障和籽晶层上形成电介质，然后形成 电介质上的金属层。 铜屏障和种子层形成电容器的底板，并且金属层形成通过电介质与底板分离的上板。 通过从铜屏障和种子层形成底板，实现了降低的薄层电阻和表面粗糙度，这两者都增强了电容器的性能。 通过形成具有镶嵌结构的电容器来进一步增强该性能。 优选地，与电容器的形成同时形成至少一个导电互连。 至少部分地通过使用平板穿透技术形成互连来实现这一点。 然后使用一个且仅一个平面化（例如CMP）步骤来完成互连和电容器。 其结果是形成电容器和互连结构，其步骤远低于常规要求，这转化为成本和效率的提高。

公开(公告)号：US20040241951A1

公开(公告)日：2004-12-02

申请号：US10727946

申请日：2003-12-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey R. Amadon ,  Anil K. Chinthakindi ,  Kenneth J. Stein ,  Kwong H. Wong

IPC: H01L021/8234 ,  H01L021/8244 ,  H01L021/20

CPC classification number: H01C7/06 ,  H01C7/006

Abstract: A thin film resistor that has a substantially zero TCR is provided as well as a method for fabricating the same. The thin film resistor includes at least two resistor materials located over one another. Each resistor material has a different temperature coefficient of resistivity such that the effective temperature coefficient of resistivity of the thin film resistor is substantially 0 ppm/null C. The thin film resistor may be integrated into a interconnect structure or it may be integrated with a metal-insulator-metal capacitor (MIMCAP).

Abstract translation: 提供具有基本为零TCR的薄膜电阻器及其制造方法。 薄膜电阻器包括彼此位于的至少两个电阻材料。 每个电阻器材料具有不同的电阻率温度系数，使得薄膜电阻器的电阻率的有效温度系数基本上为0ppm /℃。薄膜电阻器可以集成到互连结构中，或者可以与金属 - 绝缘体 - 金属电容器（MIMCAP）。

公开(公告)号：US20040239478A1

公开(公告)日：2004-12-02

申请号：US10250075

申请日：2003-06-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey R. Amadon ,  Anil K. Chinthakindi ,  Kenneth J. Stein ,  Kwong H. Wong

IPC: H01C007/06

CPC classification number: H01C7/06 ,  H01C7/006

Abstract: A thin film resistor that has a substantially zero TCR is provided as well as a method for fabricating the same. The thin film resistor includes at least two resistor materials located over one another. Each resistor material has a different temperature coefficient of resistivity such that the effective temperature coefficient of resistivity of the thin film resistor is substantially 0 ppm/null C. The thin film resistor may be integrated into a interconnect structure or it may be integrated with a metal-insulator-metal capacitor (MIMCAP).

Abstract translation: 提供具有基本为零TCR的薄膜电阻器及其制造方法。 薄膜电阻器包括彼此位于的至少两个电阻材料。 每个电阻器材料具有不同的电阻率温度系数，使得薄膜电阻器的电阻率的有效温度系数基本上为0ppm /℃。薄膜电阻器可以集成到互连结构中，或者可以与金属 - 绝缘体 - 金属电容器（MIMCAP）。

公开(公告)号：US20040224494A1

公开(公告)日：2004-11-11

申请号：US10249799

申请日：2003-05-08

Applicant: International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  Stephen E. Greco ,  Keith T. Kwietniak ,  Soon-Cheon Seo ,  Chih-Chao Yang ,  Yun-Yu Wang ,  Kwong H. Wong

IPC: H01L021/4763

CPC classification number: H01L21/76843 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76835 ,  H01L21/76856 ,  H01L2221/1036

Abstract: The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features. The insulator includes pores along surface areas of the insulator that are in contact with the liner and the pores exist only along the surface areas that are in contact with the liner (the liner is not within the pores).

Abstract translation: 本发明提供一种形成集成电路结构中的布线层的方法，该集成电路结构形成有机绝缘体，图案化绝缘体，将衬垫沉积在绝缘体上，并将该结构暴露于等离子体，以在绝缘体旁边的区域中形成孔 衬垫。 衬垫形成得足够薄以允许等离子体穿过衬垫并在绝缘体中形成孔。 在等离子体处理期间，等离子体通过衬垫而不影响衬垫。 在等离子体处理之后，可以沉积另外的衬里材料。 此后，导体被沉积，导体的多余部分从结构中移除，使得导体仅保留在绝缘体的图案化部分内。 该方法产生集成电路结构，其具有具有图案化特征的有机绝缘体，衬里图案化特征的衬垫和填充图案化特征的导体。 绝缘体包括与绝缘体的表面区域相接触的孔，该孔与衬垫接触，并且孔仅沿着与衬垫接触的表面区域（衬里不在孔内）存在。