公开(公告)号：US20020197807A1

公开(公告)日：2002-12-26

申请号：US09885792

申请日：2001-06-20

Applicant: International Business Machines Corporation

Inventor： Basanth Jagannathan ,  Shwu-Jen Jeng ,  Jeffrey B. Johnson ,  Robb A. Johnson ,  Louis D. Lanzerotti ,  Kenneth J. Stein ,  Seshadri Subbanna

IPC: H01L021/331 ,  H01L021/8222

CPC classification number: H01L29/66242 ,  H01L21/8249 ,  H01L29/7378

Abstract: A method for making a non-self-aligned, heterojunction bipolar transistor includes forming extrinsic base regions with a PFET source/drain implant aligned with the polysilicon in an emitter stack but which are not directly aligned with an emitter opening defined in that stack. This is achieved by making the emitter pedestal wider than the emitter opening. This advantageously removes the dependency of alignment between the extrinsic base regions and the emitter opening, thereby resulting in fewer process steps, reduced thermal cycles, and improved speed.

Abstract translation: 用于制造非自对准异质结双极晶体管的方法包括：在发射极堆叠中与多晶硅对准的PFET源极/漏极注入形成非本征基极区域，但不直接对准在该叠层中限定的发射极开口。 这通过使发射器基座宽于发射器开口来实现。 这有利地消除了非本征基区和发射极开口之间的对准的依赖性，从而导致更少的工艺步骤，减少的热循环和改进的速度。

公开(公告)号：US20040130434A1

公开(公告)日：2004-07-08

申请号：US10336992

申请日：2003-01-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anil K. Chinthakindi ,  Shwu-Jen Jeng ,  Michael F. Lofaro ,  Christopher M. Schnabel ,  Kenneth J. Stein

IPC: H01C001/012

CPC classification number: H01L28/20 ,  H01L23/5223 ,  H01L27/0802 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  Y10S438/97 ,  Y10T29/49082 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A method is disclosed of fabricating a MIMCAP (a capacitor (CAP) formed by successive layers of metal, insulator, metal (MIM)) and a thin film resistor at the same level. A method is also disclosed of fabricating a MIMCAP and a thin film resistor at the same level, and a novel integration scheme for BEOL (back-end-of-line processing) thin film resistors which positions them closer to FEOL (front-end-of-line processing) devices.

Abstract translation: 公开了制造MIMCAP（由金属，绝缘体，金属（MIM）的连续层形成的电容器（CAP））和同一水平的薄膜电阻器的方法。 还公开了制造相同水平的MIMCAP和薄膜电阻器的方法，以及用于BEOL（后端处理）薄膜电阻器的新颖的集成方案，使它们更接近FEOL（前端 - 线上处理）设备。

公开(公告)号：US20040104420A1

公开(公告)日：2004-06-03

申请号：US10249550

申请日：2003-04-17

Applicant: International Business Machines Corporation

Inventor： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Joseph F. Shepard JR. ,  Kenneth J. Stein ,  Kunal Vaed

IPC: H01L029/76

CPC classification number: H01L28/40 ,  H01L21/31604 ,  H01L28/55

Abstract: The present invention provides a high-performance metal-insulator-metal (MIM) capacitor which contains a high-k dielectric, yet no substantial shorting of the MIM capacitor is observed. Specifically, shorting of the MIM capacitor is substantially prevented in the present invention by forming a passivation layer between the high-k dielectric layer and each of the capacitornulls electrodes. The inventive MIM capacitor includes a first conductor; a first passivation layer located atop the first conductor; a high-k dielectric layer located atop the first passivation layer; a second passivation layer located atop the high k dielectric layer; and a second conductor located atop the second passivation layer.

Abstract translation: 本发明提供了一种高性能金属绝缘体金属（MIM）电容器，其包含高k电介质，但没有观察到MIM电容器的实质短路。 具体地说，在本发明中通过在高k电介质层和电容器电极之间形成钝化层，实质上防止了MIM电容器的短路，本发明的MIM电容器包括：第一导体;位于顶部的第一钝化层 所述第一导体;位于所述第一钝化层顶部的高k电介质层;位于所述高k电介质层顶部的第二钝化层;以及位于所述第二钝化层顶部的第二导体。

公开(公告)号：US20030178635A1

公开(公告)日：2003-09-25

申请号：US10104972

申请日：2002-03-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Richard P. Volant ,  Robert A. Groves ,  Kevin S. Petrarca ,  David M. Rockwell ,  Kenneth J. Stein

IPC: H01L029/74

CPC classification number: H01H59/0009 ,  B81B3/0021 ,  B81B2201/018 ,  B81B2203/058 ,  B81B2207/015 ,  B81C1/00214 ,  H01H2001/0068 ,  H01H2059/0054

Abstract: A semiconductor torsional micro-electromechanical (MEM) switch is described having a conductive movable control electrode; an insulated semiconductor torsion beam attached to the movable control electrode, the insulated torsion beam and the movable control electrode being parallel to each other; and a movable contact attached to the insulated torsion beam, wherein the combination of the insulated torsion beam and the control electrode is perpendicular to the movable contact. The torsional MEM switch is characterized by having its control electrodes substantially perpendicular to the switching electrodes. The MEM switch may also include multiple controls to activate the device to form a single-pole, single-throw switch or a multiple-pole, multiple-throw switch. The method of fabricating the torsional MEM switch is fully compatible with the CMOS manufacturing process.

Abstract translation: 描述了具有导电可移动控制电极的半导体扭转微机电（MEM）开关; 连接到可移动控制电极的绝缘半导体扭转梁，绝缘扭转梁和可移动控制电极彼此平行; 以及连接到所述绝缘扭力梁的可动触头，其中所述绝缘扭转梁和所述控制电极的组合垂直于所述可动触头。 扭转MEM开关的特征在于其控制电极基本上垂直于开关电极。 MEM开关还可以包括多个控制以激活该装置以形成单极单掷开关或多极多掷开关。 制造扭转MEM开关的方法与CMOS制造工艺完全兼容。

公开(公告)号：US20030148550A1

公开(公告)日：2003-08-07

申请号：US10014660

申请日：2001-11-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Richard P. Volant ,  John C. Bisson ,  Donna R. Cote ,  Timothy J. Dalton ,  Robert A. Groves ,  Kevin S. Petrarca ,  Kenneth J. Stein ,  Seshadri Subbanna

IPC: H01L021/00

CPC classification number: B81C1/00246 ,  B81B2201/016 ,  B81B2201/018 ,  B81B2203/0127 ,  B81B2207/07 ,  B81C1/00611 ,  B81C2201/0122 ,  B81C2203/0735 ,  H01G5/40 ,  H01H59/0009

Abstract: A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.

Abstract translation: 描述了使用兼容工艺和材料制造与常规半导体互连级别集成的微机电开关（MEMS）的方法。 该方法基于制造容易修改以产生用于接触切换和任何数量的金属 - 介电金属开关的各种配置的电容开关。 该过程开始于铜镶嵌互连层，由金属导体嵌入电介质中。 铜互连的全部或部分凹陷到足以在开关处于闭合状态时提供电容气隙的程度，并为例如Ta / TaN的保护层提供空间。 在为开关指定的区域内限定的金属结构用作致动器电极以下拉可移动光束并且提供一个或多个路径用于开关信号横越。 气隙的优点是空气不会受到可能导致可靠性和电压漂移问题的电荷储存或捕集。 代替使电极凹陷以提供间隙，可以仅在电极上或周围添加电介质。 下一层是另一介质层，其被沉积到形成在下电极和形成开关器件的可移动梁之间的间隙的期望厚度上。 通过该电介质制造通孔以提供金属互连层和还包含可切换光束的下一个金属层之间的连接。 然后对通孔层进行图案化和蚀刻以提供包含下部激活电极以及信号路径的空腔区域。 然后用牺牲脱模材料填充空腔。 然后将该释放材料与电介质的顶部平坦化，由此提供构造波束层的平坦表面。

公开(公告)号：US20030116850A1

公开(公告)日：2003-06-26

申请号：US10026146

申请日：2001-12-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Richard P. Volant ,  Seshadri Subbanna ,  Robert A. Groves ,  John C. Malinowski ,  Kenneth J. Stein ,  Kevin S. Petrarca

IPC: H01L023/48

CPC classification number: H01L23/66 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A passive electrical device includes a first electrical conductor, a second electrical conductor disposed over the first conductor; and a third electrical conductor connecting the first conductor to the second conductor. The said first, second and third conductors are disposed on a semiconductor substrate. The sheet resistivity of the first conductor is approximately equal to the sheet resistivity of the second conductor.

Abstract translation: 无源电气装置包括第一电导体，布置在第一导体上的第二电导体; 以及将第一导体连接到第二导体的第三电导体。 所述第一，第二和第三导体设置在半导体衬底上。 第一导体的薄层电阻率近似等于第二导体的薄层电阻率。

公开(公告)号：US20030057458A1

公开(公告)日：2003-03-27

申请号：US09962738

申请日：2001-09-25

Applicant: International Business Machines Corporation

Inventor： Gregory G. Freeman ,  Seshadri Subbanna ,  Basanth Jagannathan ,  Kathryn T. Schonenberg ,  Shwu-Jen Jeng ,  Kenneth J. Stein ,  Jeffrey B. Johnson

IPC: H01L029/80 ,  H01L031/112

CPC classification number: H01L29/66242 ,  H01L29/1004 ,  H01L29/7378

Abstract: A raised extrinsic base, silicon germanium (SiGe) heterojunction bipolar transistor (HBT), and a method of making the same is disclosed herein. The heterojunction bipolar transistor includes a substrate, a silicon germanium layer formed on the substrate, a collector layer formed on the substrate, a raised extrinsic base layer formed on the silicon germanium layer, and an emitter layer formed on the silicon germanium layer. The silicon germanium layer forms a heterojunction between the emitter layer and the raised extrinsic base layer. The bipolar transistor further includes a base electrode formed on a portion of the raised extrinsic base layer, a collector electrode formed on a portion of the collector layer, and an emitter electrode formed on a portion of the emitter layer. Thus, the heterojunction bipolar transistor includes a self-aligned raised extrinsic base, a minimal junction depth, and minimal interstitial defects influencing the base width, all being formed with minimal thermal processing. The heterojunction bipolar transistor simultaneously improves three factors that affect the speed and performance of bipolar transistors: base width, base resistance, and base-collector capacitance.

Abstract translation: 本文公开了一种凸起的外在基极，硅锗（SiGe）异质结双极晶体管（HBT）及其制造方法。 异质结双极晶体管包括基板，形成在基板上的硅锗层，形成在基板上的集电极层，形成在硅锗层上的升高的非本征基极层和形成在硅锗层上的发射极层。 硅锗层在发射极层和凸起的非本征基极层之间形成异质结。 双极晶体管还包括形成在凸起的非本征基极层的一部分上的基极，在集电极层的一部分上形成的集电极，以及形成在发射极层的一部分上的发射极。 因此，异质结双极晶体管包括自对准凸起的外在基极，最小结深度以及影响基底宽度的最小间隙缺陷，全部以最小的热处理形成。 异质结双极晶体管同时改善了影响双极晶体管速度和性能的三个因素：基极宽度，基极电阻和基极集电极电容。

公开(公告)号：US20020094656A1

公开(公告)日：2002-07-18

申请号：US09764832

申请日：2001-01-17

Applicant: International Business Machines Corporation

Inventor： Michael D. Armacost ,  Andreas K. Augustin ,  Gerald R. Friese ,  John E. Heidenreich III ,  Gary R. Hueckel ,  Kenneth J. Stein

IPC: H01L021/20 ,  H01L021/44

CPC classification number: H01L28/40 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/76802 ,  H01L21/76816 ,  H01L23/5223 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A parallel plate capacitor in copper technology is formed in an area that has no copper below it (within 0.3 nullm) with a bottom etch stop layer, a composite bottom plate having an aluminum layer below a TiN layer, an oxide capacitor dielectric, and a top plate of TiN; in a process that involves etching the top plate to leave a capacitor area, etching the bottom plate to a larger bottom area having a margin on all sides; depositing an interlayer dielectric having a higher material quality below the top surface of the capacitor top plate; opening contact apertures to the top and bottom plates and to lower interconnect to a two step process that partially opens a nitride cap layer on the lower interconnect and the top plate while penetrating the nitride cap layer above the bottom plate, then cutting through the capacitor dielectric and finishing the penetration of the nitride cap layer.

Abstract translation: 在铜技术中的平行平板电容器形成在其下方没有铜（0.3μm以下）的区域中，底部蚀刻停止层，在TiN层下方具有铝层的复合底板，氧化物电容器电介质和 TiN顶板; 在包括蚀刻顶板以留下电容器区域的过程中，将底板蚀刻到具有在所有侧面上的边缘的较大底部区域; 在电容器顶板的顶表面下沉积具有较高材料质量的层间电介质; 打开接触孔到顶板和底板，并且将互连件下降到两步工艺，其在穿过底板上方的氮化物盖层之后部分地打开下互连和顶板上的氮化物盖层，然后切穿电容器电介质 并完成氮化物盖层的穿透。

公开(公告)号：US20040241951A1

公开(公告)日：2004-12-02

申请号：US10727946

申请日：2003-12-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey R. Amadon ,  Anil K. Chinthakindi ,  Kenneth J. Stein ,  Kwong H. Wong

IPC: H01L021/8234 ,  H01L021/8244 ,  H01L021/20

CPC classification number: H01C7/06 ,  H01C7/006

Abstract: A thin film resistor that has a substantially zero TCR is provided as well as a method for fabricating the same. The thin film resistor includes at least two resistor materials located over one another. Each resistor material has a different temperature coefficient of resistivity such that the effective temperature coefficient of resistivity of the thin film resistor is substantially 0 ppm/null C. The thin film resistor may be integrated into a interconnect structure or it may be integrated with a metal-insulator-metal capacitor (MIMCAP).

Abstract translation: 提供具有基本为零TCR的薄膜电阻器及其制造方法。 薄膜电阻器包括彼此位于的至少两个电阻材料。 每个电阻器材料具有不同的电阻率温度系数，使得薄膜电阻器的电阻率的有效温度系数基本上为0ppm /℃。薄膜电阻器可以集成到互连结构中，或者可以与金属 - 绝缘体 - 金属电容器（MIMCAP）。

公开(公告)号：US20040239478A1

公开(公告)日：2004-12-02

申请号：US10250075

申请日：2003-06-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey R. Amadon ,  Anil K. Chinthakindi ,  Kenneth J. Stein ,  Kwong H. Wong

IPC: H01C007/06

CPC classification number: H01C7/06 ,  H01C7/006

Abstract: A thin film resistor that has a substantially zero TCR is provided as well as a method for fabricating the same. The thin film resistor includes at least two resistor materials located over one another. Each resistor material has a different temperature coefficient of resistivity such that the effective temperature coefficient of resistivity of the thin film resistor is substantially 0 ppm/null C. The thin film resistor may be integrated into a interconnect structure or it may be integrated with a metal-insulator-metal capacitor (MIMCAP).

Abstract translation: 提供具有基本为零TCR的薄膜电阻器及其制造方法。 薄膜电阻器包括彼此位于的至少两个电阻材料。 每个电阻器材料具有不同的电阻率温度系数，使得薄膜电阻器的电阻率的有效温度系数基本上为0ppm /℃。薄膜电阻器可以集成到互连结构中，或者可以与金属 - 绝缘体 - 金属电容器（MIMCAP）。