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    Automated synthesis of high-performance two operand binary parallel prefix adder
    1.
    发明授权
    Automated synthesis of high-performance two operand binary parallel prefix adder 失效
    自动合成高性能两个操作数二进制并行前缀加法器

    公开(公告)号：US08527920B1

    公开(公告)日：2013-09-03

    申请号：US13752934

    申请日：2013-01-29

    Applicant: International Business Machines Corporation

    Inventor： Mihir Choudhury ,  Ruchir Puri ,  Subhendu Roy ,  Sharad C. Sundararajan

    IPC: G06F17/50

    CPC classification number: G06F17/505

    Abstract: A method for automated synthesis of a parallel prefix device includes determining structural constraints for a given parallel prefix device; generating a plurality of candidate prefix graphs for the parallel prefix device by performing a search of possible prefix graphs meeting the constraints; performing physical synthesis of each of the plurality of candidate prefix graphs to generate performance information for each candidate prefix graph; and determining one or more of the plurality of candidate prefix graphs that meet performance criteria for incorporation into the parallel prefix device.

    Abstract translation: 一种用于并行前缀设备的自动合成的方法包括确定给定并行前缀设备的结构约束; 通过执行满足约束的可能的前缀图形的搜索来生成用于并行前缀设备的多个候选前缀图; 执行所述多个候选前缀图形中的每一个的物理合成以产生每个候选前缀图表的性能信息; 以及确定满足用于并入所述并行前缀设备的性能标准的所述多个候选前缀图表中的一个或多个。

    ENTITY STANDARDIZATION FOR APPLICATION MODERNIZATION
    2.
    发明公开
    ENTITY STANDARDIZATION FOR APPLICATION MODERNIZATION 审中-公开

    公开(公告)号：US20240256852A1

    公开(公告)日：2024-08-01

    申请号：US18160301

    申请日：2023-01-26

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Jiaqing Yuan ,  Michele Merler ,  Mihir Choudhury ,  Venkata Nagaraju Pavuluri ,  Maja Vukovic

    IPC: G06N3/08 ,  G06N5/022

    CPC classification number: G06N3/08 ,  G06N5/022

    Abstract: Standardizing a mention of an application component in a free-form text describing the technology stack of the application includes extracting the mention and encoding the mention with an embedding space encoder. The encoding creates an encoded representation of the mention in a multi-dimensional embedding space. The embedding space encoder implements a machine learning model trained using contrastive learning. The encoded representation of the mention is mapped to an encoded representation of an entity in the multi-dimensional embedding space, the entity extracted from a knowledge base of computer components. The entity whose encoded representation maps to the encoded representation of the mention can be output responsive to the mapping.

    Automated region based optimization of chip manufacture
    3.
    发明授权
    Automated region based optimization of chip manufacture 有权

    公开(公告)号：US10776543B2

    公开(公告)日：2020-09-15

    申请号：US16017126

    申请日：2018-06-25

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Josiah Hamilton ,  David J. Geiger ,  Mihir Choudhury ,  Alexander J. Suess

    IPC: G06F30/392 ,  G06F30/394 ,  G06F30/327 ,  G06F30/398 ,  G06F119/12

    Abstract: Technical solutions are described herein for fabrication of a chip with optimized chip design during the logical synthesis phase of the fabrication. An example method includes optimizing, by a physical synthesis system, a chip design for a chip to be fabricated, the optimization performed according to a first performance metric for the entire chip. The method further includes receiving, by the physical synthesis system, a feedback input comprising a region of the chip and a second performance metric associated with the region. The method further includes modifying, by the physical synthesis system, the chip design by optimizing the region of the chip according to the second performance metric. The method further includes sending, by the physical synthesis system, the modified chip design for fabrication of the chip.

    Building of Custom Convolution Filter for a Neural Network Using an Automated Evolutionary Process
    4.
    发明申请
    Building of Custom Convolution Filter for a Neural Network Using an Automated Evolutionary Process 有权

    公开(公告)号：US20210174175A1

    公开(公告)日：2021-06-10

    申请号：US16705488

    申请日：2019-12-06

    Applicant: International Business Machines Corporation

    Inventor： Mihir Choudhury ,  Atin Sood ,  Ruchir Puri

    IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08

    Abstract: Mechanisms are provided for synthesizing a computer implemented neural network. An initially trained neural network is received and modified by introducing a new hidden layer of neurons and new connections that connect the new hidden layer of neurons to an output layer and a previous layer of neurons previously directly connected to the output layer of neurons to generate a modified neural network. The modified neural network is trained through one or more epochs of machine learning to generate modified weight values for the new connections and the new connections are pruned based on the modified weight values to remove a subset of the new connections and leaving remaining connections in the modified neural network. A merge operation is performed on the remaining connections in the modified neural network to generate a custom convolution filter and modified neural network. The modified neural network is then retrained for deployment.

    Automated synthesis of high-performance two operand binary parallel prefix adder
    5.
    发明授权
    Automated synthesis of high-performance two operand binary parallel prefix adder 失效
    自动合成高性能两个操作数二进制并行前缀加法器

    公开(公告)号：US08683398B1

    公开(公告)日：2014-03-25

    申请号：US13686624

    申请日：2012-11-27

    Applicant: International Business Machines Corporation

    Inventor： Mihir Choudhury ,  Ruchir Puri ,  Subhendu Roy ,  Sharad C. Sundararajan

    IPC: G06F17/50

    CPC classification number: G06F17/505

    Abstract: A method for automated synthesis of a parallel prefix device includes determining structural constraints for a given parallel prefix device; generating a plurality of candidate prefix graphs for the parallel prefix device by performing a search of possible prefix graphs meeting the constraints; performing physical synthesis of each of the plurality of candidate prefix graphs to generate performance information for each candidate prefix graph; and determining one or more of the plurality of candidate prefix graphs that meet performance criteria for incorporation into the parallel prefix device.

    Abstract translation: 一种用于并行前缀设备的自动合成的方法包括确定给定并行前缀设备的结构约束; 通过执行满足约束的可能的前缀图形的搜索来生成用于并行前缀设备的多个候选前缀图; 执行所述多个候选前缀图形中的每一个的物理合成以产生每个候选前缀图表的性能信息; 以及确定满足用于并入所述并行前缀设备的性能标准的所述多个候选前缀图表中的一个或多个。

    AUTOMATED REGION BASED OPTIMIZATION OF CHIP MANUFACTURE
    6.
    发明申请
    AUTOMATED REGION BASED OPTIMIZATION OF CHIP MANUFACTURE 审中-公开

    公开(公告)号：US20190392089A1

    公开(公告)日：2019-12-26

    申请号：US16017126

    申请日：2018-06-25

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Josiah Hamilton ,  David J. Geiger ,  Mihir Choudhury ,  Alexander J. Suess

    IPC: G06F17/50

    Abstract: Technical solutions are described herein for fabrication of a chip with optimized chip design during the logical synthesis phase of the fabrication. An example method includes optimizing, by a physical synthesis system, a chip design for a chip to be fabricated, the optimization performed according to a first performance metric for the entire chip. The method further includes receiving, by the physical synthesis system, a feedback input comprising a region of the chip and a second performance metric associated with the region. The method further includes modifying, by the physical synthesis system, the chip design by optimizing the region of the chip according to the second performance metric. The method further includes sending, by the physical synthesis system, the modified chip design for fabrication of the chip.

    Building of custom convolution filter for a neural network using an automated evolutionary process
    10.
    发明授权
    Building of custom convolution filter for a neural network using an automated evolutionary process 有权

    公开(公告)号：US11488007B2

    公开(公告)日：2022-11-01

    申请号：US16705488

    申请日：2019-12-06

    Applicant: International Business Machines Corporation

    Inventor： Mihir Choudhury ,  Atin Sood ,  Ruchir Puri

    IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04

    Abstract: Mechanisms are provided for synthesizing a computer implemented neural network. An initially trained neural network is received and modified by introducing a new hidden layer of neurons and new connections that connect the new hidden layer of neurons to an output layer and a previous layer of neurons previously directly connected to the output layer of neurons to generate a modified neural network. The modified neural network is trained through one or more epochs of machine learning to generate modified weight values for the new connections and the new connections are pruned based on the modified weight values to remove a subset of the new connections and leaving remaining connections in the modified neural network. A merge operation is performed on the remaining connections in the modified neural network to generate a custom convolution filter and modified neural network. The modified neural network is then retrained for deployment.

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