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公开(公告)号：US20210111039A1
公开(公告)日：2021-04-15
申请号：US16601799
申请日：2019-10-15
摘要： A structure with controlled capillary coverage is provided and includes a substrate including one or more first contacts, a component and adhesive. The component includes one or more second contacts and a rib disposed at a distance from each of the one or more second contacts. The component is disposed such that the one or more second contacts are communicative with the one or more first contacts and corresponding surfaces of the substrate and the rib face each other at a controlled gap height to define a fill-space. The adhesive is dispensed at a discrete point whereby the adhesive is drawn to fill the fill-space by capillary action.
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公开(公告)号：US11031373B2
公开(公告)日：2021-06-08
申请号：US16369532
申请日：2019-03-29
发明人： Charles L. Arvin , Bhupender Singh , Richard Francis Indyk , Steve Ostrander , Thomas Weiss , Mark Kapfhammer
IPC分类号： H01L25/065 , H01L23/00 , H01L23/522 , H01L23/532
摘要： A multi-die integrated circuit device and a method of fabricating the multi-die integrated circuit device involve a substrate. Two or more dice include components that implement functionality of the multi-die integrated circuit. The components include logic gates. The multi-die integrated circuit device also includes a spacer disposed between the substrate and each of the two or more dice. Each of the two or more dice makes direct electrical contact with the substrate without making direct electrical contact with the spacer through holes in the spacer.
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公开(公告)号：US11177217B2
公开(公告)日：2021-11-16
申请号：US16738196
申请日：2020-01-09
发明人： Kamal K. Sikka , Jon A. Casey , Joshua Rubin , Arvind Kumar , Dinesh Gupta , Charles L. Arvin , Mark W. Kapfhammer , Steve Ostrander , Maryse Cournoyer , Valérie A. Oberson , Lawrence A. Clevenger
IPC分类号： H01L23/538 , H01L23/367 , H01L23/00 , H01L23/31 , H01L25/065
摘要： Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.
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公开(公告)号：US11152226B2
公开(公告)日：2021-10-19
申请号：US16601799
申请日：2019-10-15
摘要： A structure with controlled capillary coverage is provided and includes a substrate including one or more first contacts, a component and adhesive. The component includes one or more second contacts and a rib disposed at a distance from each of the one or more second contacts. The component is disposed such that the one or more second contacts are communicative with the one or more first contacts and corresponding surfaces of the substrate and the rib face each other at a controlled gap height to define a fill-space. The adhesive is dispensed at a discrete point whereby the adhesive is drawn to fill the fill-space by capillary action.
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公开(公告)号：US20200176383A1
公开(公告)日：2020-06-04
申请号：US16209013
申请日：2018-12-04
发明人： Charles L. Arvin , Brian W. Quinlan , Steve Ostrander , Thomas Weiss , Mark W. Kapfhammer , Shidong Li
IPC分类号： H01L23/538 , H01L25/065 , H01L23/00 , H01L23/31 , H01L23/373 , H01L25/00 , H01L21/48 , H01L21/56
摘要： A multiple chip carrier assembly including a carrier having a first surface and a second surface is attached to a plurality of chips is described. The plurality of chips include a first chip and a second chip. Each of the chips has first surface with a first set of solder balls for connecting to a package and a second set of solder balls for connecting to a high signal density bridge element. A second surface of each chip is bonded to the first surface of the carrier. A package has a first surface which is connected to the first sets of solder balls of the first and second chips. A high signal density bridge element having high signal density wiring on one or more layers is connected to the second sets of solder balls of the first and second chips. The bridge element is disposed between the first surface of the package and the first surfaces of the first and second chips.
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公开(公告)号：US20190295952A1
公开(公告)日：2019-09-26
申请号：US15926044
申请日：2018-03-20
发明人： Kamal K. Sikka , Jon A. Casey , Joshua Rubin , Arvind Kumar , Dinesh Gupta , Charles L. Arvin , Mark W. Kapfhammer , Steve Ostrander , Maryse Cournoyer , Valérie A. Oberson , Lawrence A. Clevenger
IPC分类号： H01L23/538 , H01L23/367 , H01L23/00 , H01L23/31 , H01L25/065
摘要： Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.
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公开(公告)号：US10985129B2
公开(公告)日：2021-04-20
申请号：US16384148
申请日：2019-04-15
摘要： Multiple integrated circuit (IC) devices are connected to a top side metallization surface of a multi IC device carrier. The carrier includes resin based substrate layers and associated wiring line layers. To reduce stain of the resin layers, especially in region(s) within the carrier between the IC devices, a stiffener or stiffeners are applied to the back side metallization (BSM) surface of the IC device carrier. The stiffener(s) reduce the amount of curvature of the IC device carrier and reduce the strain seen by the resin layer(s), thereby mitigating the risk for cracks forming and expanding within the resin layers.
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公开(公告)号：US10916507B2
公开(公告)日：2021-02-09
申请号：US16209013
申请日：2018-12-04
发明人： Charles L Arvin , Brian W Quinlan , Steve Ostrander , Thomas Weiss , Mark W Kapfhammer , Shidong Li
IPC分类号： H01L23/538 , H01L25/065 , H01L23/00 , H01L23/31 , H01L23/373 , H01L25/00 , H01L21/48 , H01L21/56
摘要： A multiple chip carrier assembly including a carrier having a first surface and a second surface is attached to a plurality of chips is described. The plurality of chips include a first chip and a second chip. Each of the chips has first surface with a first set of solder balls for connecting to a package and a second set of solder balls for connecting to a high signal density bridge element. A second surface of each chip is bonded to the first surface of the carrier. A package has a first surface which is connected to the first sets of solder balls of the first and second chips. A high signal density bridge element having high signal density wiring on one or more layers is connected to the second sets of solder balls of the first and second chips. The bridge element is disposed between the first surface of the package and the first surfaces of the first and second chips.
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公开(公告)号：US20200328177A1
公开(公告)日：2020-10-15
申请号：US16384148
申请日：2019-04-15
摘要： Multiple integrated circuit (IC) devices are connected to a top side metallization surface of a multi IC device carrier. The carrier includes resin based substrate layers and associated wiring line layers. To reduce stain of the resin layers, especially in region(s) within the carrier between the IC devices, a stiffener or stiffeners are applied to the back side metallization (BSM) surface of the IC device carrier. The stiffener(s) reduce the amount of curvature of the IC device carrier and reduce the strain seen by the resin layer(s), thereby mitigating the risk for cracks forming and expanding within the resin layers.
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公开(公告)号：US20200312812A1
公开(公告)日：2020-10-01
申请号：US16369532
申请日：2019-03-29
发明人： Charles L. Arvin , Bhupender Singh , Richard Francis Indyk , Steve Ostrander , Thomas Weiss , Mark Kapfhammer
IPC分类号： H01L25/065 , H01L23/00 , H01L23/532 , H01L23/522
摘要： A multi-die integrated circuit device and a method of fabricating the multi-die integrated circuit device involve a substrate. Two or more dice include components that implement functionality of the multi-die integrated circuit. The components include logic gates. The multi-die integrated circuit device also includes a spacer disposed between the substrate and each of the two or more dice. Each of the two or more dice makes direct electrical contact with the substrate without making direct electrical contact with the spacer through holes in the spacer.
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