公开(公告)号：US20170170148A1

公开(公告)日：2017-06-15

申请号：US14969905

申请日：2015-12-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin V. Fasano ,  Mark W. Kapfhammer ,  David J. Lewison ,  Thomas E. Lombardi ,  Thomas Weiss

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/06513

Abstract: A technique relates to forming a chip assembly. Top and bottom chip stack elements containing solder pads and a solder material are provided. Soluble standoffs are applied to the bottom chip stack element. The chip stack elements are aligned to bring the top solder pad in proximity to the bottom solder pad and the temperature is raised to a temperature above the melting temperature of the solder material to form a connected chip assembly. The connected chip assembly is cooled to re-solidify the solder material and soluble standoffs are removed from the connected chip assembly.

公开(公告)号：US10580738B2

公开(公告)日：2020-03-03

申请号：US15926044

申请日：2018-03-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kamal K. Sikka ,  Jon A. Casey ,  Joshua Rubin ,  Arvind Kumar ,  Dinesh Gupta ,  Charles L. Arvin ,  Mark W. Kapfhammer ,  Steve Ostrander ,  Maryse Cournoyer ,  Valérie A. Oberson ,  Lawrence A. Clevenger

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/36 ,  H01L25/065 ,  H01L23/367 ,  H01L23/00

Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.

公开(公告)号：US10431563B1

公开(公告)日：2019-10-01

申请号：US15948038

申请日：2018-04-09

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Mark W. Kapfhammer ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Thomas Weiss

IPC: H01L23/52 ,  H01L21/56 ,  H01L23/40 ,  H01L23/34 ,  H01L23/522 ,  H01L25/065 ,  H01L25/00 ,  H01L23/13 ,  H01L23/538 ,  H01L23/00

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

公开(公告)号：US10892249B2

公开(公告)日：2021-01-12

申请号：US16427631

申请日：2019-05-31

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Mark W. Kapfhammer ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Thomas Weiss

IPC: H01L23/52 ,  H01L21/56 ,  H01L23/40 ,  H01L23/34 ,  H01L23/522 ,  H01L25/065 ,  H01L25/00 ,  H01L23/13 ,  H01L23/538 ,  H01L23/00

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

公开(公告)号：US20190312011A1

公开(公告)日：2019-10-10

申请号：US16427631

申请日：2019-05-31

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Mark W. Kapfhammer ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Thomas Weiss

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L23/13

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

公开(公告)号：US09673177B1

公开(公告)日：2017-06-06

申请号：US14969905

申请日：2015-12-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin V. Fasano ,  Mark W. Kapfhammer ,  David J. Lewison ,  Thomas E. Lombardi ,  Thomas Weiss

IPC: H01L23/31 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/06513

Abstract: A technique relates to forming a chip assembly. Top and bottom chip stack elements containing solder pads and a solder material are provided. Soluble standoffs are applied to the bottom chip stack element. The chip stack elements are aligned to bring the top solder pad in proximity to the bottom solder pad and the temperature is raised to a temperature above the melting temperature of the solder material to form a connected chip assembly. The connected chip assembly is cooled to re-solidify the solder material and soluble standoffs are removed from the connected chip assembly.

公开(公告)号：US11177217B2

公开(公告)日：2021-11-16

申请号：US16738196

申请日：2020-01-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kamal K. Sikka ,  Jon A. Casey ,  Joshua Rubin ,  Arvind Kumar ,  Dinesh Gupta ,  Charles L. Arvin ,  Mark W. Kapfhammer ,  Steve Ostrander ,  Maryse Cournoyer ,  Valérie A. Oberson ,  Lawrence A. Clevenger

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.

公开(公告)号：US20210104464A1

公开(公告)日：2021-04-08

申请号：US16593489

申请日：2019-10-04

Applicant: International Business Machines Corporation

Inventor： Thomas Weiss ,  Charles L. Arvin ,  Glenn A. Pomerantz ,  Rachel E. Olson ,  Mark W. Kapfhammer ,  Bhupender Singh

IPC: H01L23/538 ,  H01L21/683 ,  H01L23/498 ,  H01L23/00

Abstract: An alignment carrier, assembly and methods that enable the precise alignment and assembly of two or more semiconductor die using an interconnect bridge. The alignment carrier includes a substrate composed of a material that has a coefficient of thermal expansion that substantially matches that of an interconnect bridge. The alignment carrier further includes a plurality of solder balls located on the substrate and configured for alignment of two or more semiconductor die.

公开(公告)号：US20200176383A1

公开(公告)日：2020-06-04

申请号：US16209013

申请日：2018-12-04

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian W. Quinlan ,  Steve Ostrander ,  Thomas Weiss ,  Mark W. Kapfhammer ,  Shidong Li

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

Abstract: A multiple chip carrier assembly including a carrier having a first surface and a second surface is attached to a plurality of chips is described. The plurality of chips include a first chip and a second chip. Each of the chips has first surface with a first set of solder balls for connecting to a package and a second set of solder balls for connecting to a high signal density bridge element. A second surface of each chip is bonded to the first surface of the carrier. A package has a first surface which is connected to the first sets of solder balls of the first and second chips. A high signal density bridge element having high signal density wiring on one or more layers is connected to the second sets of solder balls of the first and second chips. The bridge element is disposed between the first surface of the package and the first surfaces of the first and second chips.

公开(公告)号：US10515929B2

公开(公告)日：2019-12-24

申请号：US15948023

申请日：2018-04-09

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Mark W. Kapfhammer ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Thomas Weiss

IPC: H01L23/52 ,  H01L21/56 ,  H01L25/065 ,  H01L23/522 ,  H01L23/13 ,  H01L25/00 ,  H01L23/538

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.