公开(公告)号：US20130196476A1

公开(公告)日：2013-08-01

申请号：US13798573

申请日：2013-03-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Roger Allen Booth, JR. ,  Victor W. C. Chan ,  Narasimhulu Kanike ,  Huiling Shang ,  Varadarajan Vidya ,  Jun Yuan

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823412

Abstract: Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.

Abstract translation: 通过选择性地去除可以用作杂质区域的外扩散阱的膜或层，形成具有不同电特性的晶体管，例如不同的开关阈值电压或不同的泄漏特性在相同的芯片或晶片上， 将诸如硼之类的杂质引入扩散槽中，使外扩散槽已经被去除时留下杂质区域基本完整。 在形成CMOS集成电路中，这种工艺允许低泄漏和低阈值晶体管的基本上最佳设计，并允许消除掩模和附加的相关工艺，特别是在使用拉伸膜来增加电子迁移率的情况下，因为拉伸膜可以 从PMOS晶体管去除拉伸膜同时从选定的NMOS晶体管中去除。

公开(公告)号：US08927361B2

公开(公告)日：2015-01-06

申请号：US13798573

申请日：2013-03-13

Applicant: International Business Machines Corporation

Inventor： Roger Allen Booth, Jr. ,  Victor W. C. Chan ,  Narasimhulu Kanike ,  Huiling Shang ,  Varadarajan Vidya ,  Jun Yuan

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/8234

CPC classification number: H01L21/823807 ,  H01L21/823412

Abstract: Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.

Abstract translation: 通过选择性地去除可以用作杂质区域的外扩散阱的膜或层，形成具有不同电特性的晶体管，例如不同的开关阈值电压或不同的泄漏特性在相同的芯片或晶片上， 将诸如硼之类的杂质引入扩散槽中，使外扩散槽已经被去除时留下杂质区域基本完整。 在形成CMOS集成电路中，这种工艺允许低泄漏和低阈值晶体管的基本上最佳设计，并允许消除掩模和附加的相关工艺，特别是在使用拉伸膜来增加电子迁移率的情况下，因为拉伸膜可以 从PMOS晶体管去除拉伸膜同时从选定的NMOS晶体管中去除。

公开(公告)号：US12218120B2

公开(公告)日：2025-02-04

申请号：US17354469

申请日：2021-06-22

Applicant: International Business Machines Corporation

Inventor： Dureseti Chidambarrao ,  Matthew Stephen Angyal ,  Noah Zamdmer ,  Varadarajan Vidya ,  James Strom ,  Grant P. Kesselring ,  Erik Unterborn

IPC: H01L27/02 ,  G06F30/392

Abstract: A structure is provided that includes a first active circuit in which at least one of areas surrounding the first active circuit includes an active circuit-containing region. A second active circuit is spaced apart from the first active circuit. The second active circuit includes a circuit mimic fill area present in at least one of the areas surrounding the second active circuit. The circuit mimic fill area substantially matches the active circuit-containing region that is adjacent to the first active circuit. The circuit mimic fill area is located on an equivalent side of the second active circuit as the active circuit-containing region that is present adjacent the first active circuit. The use of the circuit mimic fill mitigates the effects over medium range and beyond distances that cause device failure.

公开(公告)号：US20220406769A1

公开(公告)日：2022-12-22

申请号：US17354469

申请日：2021-06-22

Applicant: International Business Machines Corporation

Inventor： Dureseti Chidambarrao ,  Matthew Stephen Angyal ,  Noah Zamdmer ,  Varadarajan Vidya ,  James Strom ,  Grant P. Kesselring ,  Erik Unterborn

IPC: H01L27/02

Abstract: A structure is provided that includes a first active circuit in which at least one of areas surrounding the first active circuit includes an active circuit-containing region. A second active circuit is spaced apart from the first active circuit. The second active circuit includes a circuit mimic fill area present in at least one of the areas surrounding the second active circuit. The circuit mimic fill area substantially matches the active circuit-containing region that is adjacent to the first active circuit. The circuit mimic fill area is located on an equivalent side of the second active circuit as the active circuit-containing region that is present adjacent the first active circuit. The use of the circuit mimic fill mitigates the effects over medium range and beyond distances that cause device failure.