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    STRUCTURE FABRICATION METHOD
    6.
    发明申请
    STRUCTURE FABRICATION METHOD 有权
    结构制造方法

    公开(公告)号：US20130230960A1

    公开(公告)日：2013-09-05

    申请号：US13866162

    申请日：2013-04-19

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Brent A. Anderson ,  Victor W. C. Chan ,  Edward J. Nowak

    IPC: H01L29/66

    CPC classification number: H01L29/66477 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/28518 ,  H01L29/1083 ,  H01L29/42376 ,  H01L29/66507 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78654

    Abstract: A structure fabrication method. A provided structure includes a gate dielectric region on the substrate and a gate electrode region on the gate dielectric region. Atoms are implanted in a top portion of the gate electrode region, which expands the top portion of the gate electrode in a direction parallel to a top surface of the gate dielectric region. After the atom implantation, a conformal dielectric layer is formed on top and side walls of the gate electrode region. A dielectric spacer layer, formed on the conformal dielectric layer, is etched such that only spacer portions of the dielectric spacer layer which are under the conformal dielectric layer remain, wherein for any point of the remaining spacer portions, a straight line through that point and parallel to a reference direction intersects the conformal dielectric layer. The reference direction is perpendicular to the top surface of the gate dielectric region.

    Abstract translation: 一种结构制造方法。 所提供的结构包括衬底上的栅极电介质区域和栅极电介质区域上的栅电极区域。 原子被注入到栅极电极区域的顶部，该栅极电极区域的顶部在与栅极电介质区域的顶表面平行的方向上扩展栅电极的顶部。 在原子注入之后，在栅电极区域的顶壁和侧壁上形成共形绝缘层。 蚀刻形成在保形电介质层上的电介质间隔层，使得仅保留在保形绝缘层之下的电介质隔离层的间隔部分，其中对于剩余间隔部分的任何点，通过该点和 平行于参考方向与保形电介质层相交。 参考方向垂直于栅介质区域的顶表面。

    HIGH THRESHOLD VOLTAGE NMOS TRANSISTORS FOR LOW POWER IC TECHNOLOGY
    7.
    发明申请
    HIGH THRESHOLD VOLTAGE NMOS TRANSISTORS FOR LOW POWER IC TECHNOLOGY 有权
    低功耗IC技术的高阈值电压NMOS晶体管

    公开(公告)号：US20130196476A1

    公开(公告)日：2013-08-01

    申请号：US13798573

    申请日：2013-03-13

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Roger Allen Booth, JR. ,  Victor W. C. Chan ,  Narasimhulu Kanike ,  Huiling Shang ,  Varadarajan Vidya ,  Jun Yuan

    IPC: H01L21/8238

    CPC classification number: H01L21/823807 ,  H01L21/823412

    Abstract: Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.

    Abstract translation: 通过选择性地去除可以用作杂质区域的外扩散阱的膜或层，形成具有不同电特性的晶体管，例如不同的开关阈值电压或不同的泄漏特性在相同的芯片或晶片上， 将诸如硼之类的杂质引入扩散槽中，使外扩散槽已经被去除时留下杂质区域基本完整。 在形成CMOS集成电路中，这种工艺允许低泄漏和低阈值晶体管的基本上最佳设计，并允许消除掩模和附加的相关工艺，特别是在使用拉伸膜来增加电子迁移率的情况下，因为拉伸膜可以 从PMOS晶体管去除拉伸膜同时从选定的NMOS晶体管中去除。

    Avoiding gate metal via shorting to source or drain contacts
    9.
    发明授权
    Avoiding gate metal via shorting to source or drain contacts 有权

    公开(公告)号：US10043744B2

    公开(公告)日：2018-08-07

    申请号：US15800154

    申请日：2017-11-01

    Applicant: International Business Machines Corporation

    Inventor： Victor W. C. Chan ,  Xuefeng Liu ,  Yann A. M. Mignot ,  Yongan Xu

    IPC: H01L23/528 ,  H01L23/522 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768

    Abstract: Techniques relate to forming a gate metal via. A gate contact has a bottom part in a first layer. A cap layer is formed on the gate contact and first layer. The gate contact is formed on top of the gate. A second layer is formed on the cap layer. The second layer and cap layer are recessed to remove a portion of the cap layer from a top part and upper sidewall parts of the gate contact. A third layer is formed on the second layer, cap layer, and gate contact. The third layer is etched through to form a gate trench over the gate contact to be around the upper sidewall parts of the gate contact. The gate trench is an opening that stops on the cap layer. Gate metal via is formed on top of the gate contact and around upper sidewall parts of the gate contact.

    High threshold voltage NMOS transistors for low power IC technology
    10.
    发明授权
    High threshold voltage NMOS transistors for low power IC technology 有权
    高阈值电压NMOS晶体管，用于低功耗IC技术

    公开(公告)号：US08927361B2

    公开(公告)日：2015-01-06

    申请号：US13798573

    申请日：2013-03-13

    Applicant: International Business Machines Corporation

    Inventor： Roger Allen Booth, Jr. ,  Victor W. C. Chan ,  Narasimhulu Kanike ,  Huiling Shang ,  Varadarajan Vidya ,  Jun Yuan

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/8234

    CPC classification number: H01L21/823807 ,  H01L21/823412

    Abstract: Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.

    Abstract translation: 通过选择性地去除可以用作杂质区域的外扩散阱的膜或层，形成具有不同电特性的晶体管，例如不同的开关阈值电压或不同的泄漏特性在相同的芯片或晶片上， 将诸如硼之类的杂质引入扩散槽中，使外扩散槽已经被去除时留下杂质区域基本完整。 在形成CMOS集成电路中，这种工艺允许低泄漏和低阈值晶体管的基本上最佳设计，并允许消除掩模和附加的相关工艺，特别是在使用拉伸膜来增加电子迁移率的情况下，因为拉伸膜可以 从PMOS晶体管去除拉伸膜同时从选定的NMOS晶体管中去除。

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