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    SOURCE-DRAIN EXTENSION FORMATION IN REPLACEMENT METAL GATE TRANSISTOR DEVICE
    1.
    发明申请
    SOURCE-DRAIN EXTENSION FORMATION IN REPLACEMENT METAL GATE TRANSISTOR DEVICE 审中-公开
    替代金属栅极晶体管器件中的源极 - 漏极扩展形成

    公开(公告)号：US20130161745A1

    公开(公告)日：2013-06-27

    申请号：US13628225

    申请日：2012-09-27

    申请人： International Business Machines Corporation

    发明人： Takashi Ando ,  Huiming Bu ,  Ramachandra Divakaruni ,  Bruce B. Doris ,  Chung-Hsun Lin ,  Huiling Shang ,  Tenko Yamashita

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/268 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/78621

    摘要： In one embodiment a transistor structure includes a gate stack disposed on a surface of a semiconductor body. The gate stack has a layer of gate dielectric surrounding gate metal and overlies a channel region in the semiconductor body. The transistor structure further includes a source having a source extension region and a drain having a drain extension region formed in the semiconductor body, where each extension region has a sharp, abrupt junction that overlaps an edge of the gate stack. Also included is a punch through stopper region having an implanted dopant species beneath the channel in the semiconductor body between the source and the drain. There is also a shallow channel region having an implanted dopant species located between the punch through stopper region and the channel. Both bulk semiconductor and silicon-on-insulator transistor embodiments are described.

    摘要翻译： 在一个实施例中，晶体管结构包括设置在半导体本体的表面上的栅极堆叠。 栅极堆叠具有围绕栅极金属的栅极电介质层，并且覆盖半导体主体中的沟道区域。 晶体管结构还包括具有源极延伸区域和漏极的源极，该漏极延伸区域形成在半导体本体中，其中每个延伸区域具有与栅极叠层的边缘重叠的尖锐的突变结。 还包括在源极和漏极之间的半导体本体中的通道下方具有注入的掺杂物质的穿孔停止区域。 还存在具有位于穿通止动区域和通道之间的注入的掺杂剂物质的浅沟道区域。 描述了体半导体和绝缘体上硅晶体管实施例。

    Strained finFET with an electrically isolated channel
    4.
    发明授权
    Strained finFET with an electrically isolated channel 有权
    具有电隔离通道的应变finFET

    公开(公告)号：US09190520B2

    公开(公告)日：2015-11-17

    申请号：US14481146

    申请日：2014-09-09

    申请人： International Business Machines Corporation

    发明人： Henry K. Utomo ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Dechao Guo ,  Myung-Hee Na ,  Ravikumar Ramachandran ,  Kern Rim ,  Huiling Shang

    IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

    CPC分类号： H01L29/7855 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

    摘要： A fin structure includes an optional doped well, a disposable single crystalline semiconductor material portion, and a top semiconductor portion formed on a substrate. A disposable gate structure straddling the fin structure is formed, and end portions of the fin structure are removed to form end cavities. Doped semiconductor material portions are formed on sides of a stack of the disposable single crystalline semiconductor material portion and a channel region including the top semiconductor portion. The disposable single crystalline semiconductor material portion may be replaced with a dielectric material portion after removal of the disposable gate structure or after formation of the stack. The gate cavity is filled with a gate dielectric and a gate electrode. The channel region is stressed by the doped semiconductor material portions, and is electrically isolated from the substrate by the dielectric material portion.

    摘要翻译： 翅片结构包括可选的掺杂阱，一次性单晶半导体材料部分和形成在衬底上的顶部半导体部分。 形成跨越翅片结构的一次性栅极结构，并且去除翅片结构的端部以形成端部空腔。 掺杂的半导体材料部分形成在一次性单晶半导体材料部分的堆叠的侧部和包括顶部半导体部分的沟道区域上。 一次性单晶半导体材料部分可以在移除一次性栅极结构之后或在堆叠形成之后用介电材料部分代替。 栅极腔填充有栅极电介质和栅电极。 沟道区域被掺杂的半导体材料部分应力，并且通过电介质材料部分与衬底电隔离。

    High threshold voltage NMOS transistors for low power IC technology
    5.
    发明授权
    High threshold voltage NMOS transistors for low power IC technology 有权
    高阈值电压NMOS晶体管，用于低功耗IC技术

    公开(公告)号：US08927361B2

    公开(公告)日：2015-01-06

    申请号：US13798573

    申请日：2013-03-13

    申请人： International Business Machines Corporation

    发明人： Roger Allen Booth, Jr. ,  Victor W. C. Chan ,  Narasimhulu Kanike ,  Huiling Shang ,  Varadarajan Vidya ,  Jun Yuan

    IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L21/8234

    CPC分类号： H01L21/823807 ,  H01L21/823412

    摘要： Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.

    摘要翻译： 通过选择性地去除可以用作杂质区域的外扩散阱的膜或层，形成具有不同电特性的晶体管，例如不同的开关阈值电压或不同的泄漏特性在相同的芯片或晶片上， 将诸如硼之类的杂质引入扩散槽中，使外扩散槽已经被去除时留下杂质区域基本完整。 在形成CMOS集成电路中，这种工艺允许低泄漏和低阈值晶体管的基本上最佳设计，并允许消除掩模和附加的相关工艺，特别是在使用拉伸膜来增加电子迁移率的情况下，因为拉伸膜可以 从PMOS晶体管去除拉伸膜同时从选定的NMOS晶体管中去除。

    Semiconductor fin isolation by a well trapping fin portion
    9.
    发明授权
    Semiconductor fin isolation by a well trapping fin portion 有权
    通过捕获翅片部分的半导体翅片隔离

    公开(公告)号：US08933528B2

    公开(公告)日：2015-01-13

    申请号：US13792797

    申请日：2013-03-11

    申请人： International Business Machines Corporation

    发明人： Henry K. Utomo ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Ravikumar Ramachandran ,  Huiling Shang ,  Reinaldo A. Vega

    IPC分类号： H01L29/78 ,  H01L29/66

    CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

    摘要： A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate. The combination of the second semiconductor material and the dopant within the well trapping layer is selected such that diffusion of the dopant is limited within the well trapping layer. A device semiconductor material layer including a third semiconductor material can be epitaxially grown on the top surface of the well trapping layer. The device semiconductor material layer, the well trapping layer, and an upper portion of the bulk semiconductor substrate are patterned to form at least one semiconductor fin. Semiconductor devices formed in each semiconductor fin can be electrically isolated from the bulk semiconductor substrate by the remaining portions of the well trapping layer.

    摘要翻译： 提供了包括第一半导体材料的体半导体衬底。 包括第二半导体材料和掺杂剂的阱捕获层形成在体半导体衬底的顶表面上。 阱阱捕获层内的第二半导体材料和掺杂剂的组合被选择为使得掺杂剂的扩散受限于阱捕获层内。 包括第三半导体材料的器件半导体材料层可以在阱捕获层的顶表面上外延生长。 图案化器件半导体材料层，阱捕获层和体半导体衬底的上部以形成至少一个半导体鳍。 形成在每个半导体鳍片中的半导体器件可以通过阱捕获层的其余部分与体半导体衬底电隔离。

    SEMICONDUCTOR FIN ISOLATION BY A WELL TRAPPING FIN PORTION
    10.
    发明申请
    SEMICONDUCTOR FIN ISOLATION BY A WELL TRAPPING FIN PORTION 有权
    半导体熔融分离由一个良好的捕捉FIN部分

    公开(公告)号：US20140252479A1

    公开(公告)日：2014-09-11

    申请号：US13792797

    申请日：2013-03-11

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Henry K. Utomo ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Ravikumar Ramachandran ,  Huiling Shang ,  Reinaldo A. Vega

    IPC分类号： H01L29/78 ,  H01L29/66

    CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

    摘要： A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate. The combination of the second semiconductor material and the dopant within the well trapping layer is selected such that diffusion of the dopant is limited within the well trapping layer. A device semiconductor material layer including a third semiconductor material can be epitaxially grown on the top surface of the well trapping layer. The device semiconductor material layer, the well trapping layer, and an upper portion of the bulk semiconductor substrate are patterned to form at least one semiconductor fin. Semiconductor devices formed in each semiconductor fin can be electrically isolated from the bulk semiconductor substrate by the remaining portions of the well trapping layer.

    摘要翻译： 提供了包括第一半导体材料的体半导体衬底。 包括第二半导体材料和掺杂剂的阱捕获层形成在体半导体衬底的顶表面上。 选择阱捕获层内的第二半导体材料和掺杂剂的组合，使得掺杂剂的扩散限制在阱捕获层内。 包括第三半导体材料的器件半导体材料层可以在阱捕获层的顶表面上外延生长。 图案化器件半导体材料层，阱捕获层和体半导体衬底的上部以形成至少一个半导体鳍。 形成在每个半导体鳍片中的半导体器件可以通过阱捕获层的其余部分与体半导体衬底电隔离。