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公开(公告)号：US20220362774A1
公开(公告)日：2022-11-17
申请号：US17813954
申请日：2022-07-21
IPC分类号： B01L3/00 , B81B1/00 , B01D15/34 , G01N27/447
摘要： Microfluidic chips that can comprise thin substrates and/or a high density of vias are described herein. An apparatus comprises: a silicon device layer comprising a plurality of vias, the plurality of vias comprising greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer, and the plurality of vias extending through the silicon device layer; and a sealing layer bonded to the silicon device layer, wherein the sealing layer has greater rigidity than the silicon device layer. In some embodiments, the silicon device layer has a thickness between about 7 micrometers and about 500 micrometers while a via of the plurality of vias has a diameter between about 5 micrometers and about 5 millimeters.
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公开(公告)号：US11458474B2
公开(公告)日：2022-10-04
申请号：US15875940
申请日：2018-01-19
摘要： Microfluidic chips that can comprise thin substrates and/or a high density of vias are described herein. An apparatus comprises: a silicon device layer comprising a plurality of vias, the plurality of vias comprising greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer, and the plurality of vias extending through the silicon device layer; and a sealing layer bonded to the silicon device layer, wherein the sealing layer has greater rigidity than the silicon device layer. In some embodiments, the silicon device layer has a thickness between about 7 micrometers and about 500 micrometers while a via of the plurality of vias has a diameter between about 5 micrometers and about 5 millimeters.
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公开(公告)号：US20190224679A1
公开(公告)日：2019-07-25
申请号：US15875940
申请日：2018-01-19
IPC分类号： B01L3/00 , G01N27/447 , G01N30/60 , B01D15/34
摘要： Microfluidic chips that can comprise thin substrates and/or a high density of vias are described herein. An apparatus comprises: a silicon device layer comprising a plurality of vias, the plurality of vias comprising greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer, and the plurality of vias extending through the silicon device layer; and a sealing layer bonded to the silicon device layer, wherein the sealing layer has greater rigidity than the silicon device layer. In some embodiments, the silicon device layer has a thickness between about 7 micrometers and about 500 micrometers while a via of the plurality of vias has a diameter between about 5 micrometers and about 5 millimeters.
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4.发明申请THROUGH-SILICON VIA STRUCTURE AND METHOD FOR IMPROVING BEOL DIELECTRIC PERFORMANCE 审中-公开通过硅的结构和提高BEOL介电性能的方法公开(公告)号：US20150097274A1
公开(公告)日：2015-04-09
申请号：US14571368
申请日：2014-12-16
发明人： Christopher Collins , Mukta G. Farooq , Troy Lawrence Graves-Abe , Tze-Man Ko , William Francis Landers , Youbo Lin , Son Van Nguyen , Jennifer Ann Oakley , Deepika Priyadarshini
IPC分类号： H01L23/522 , H01L23/528 , H01L23/532
CPC分类号： H01L23/5226 , H01L21/76831 , H01L21/76898 , H01L23/528 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An improved through-silicon via (TSV) is disclosed. A semiconductor substrate has a a back-end-of-line (BEOL) stack formed thereon. The BEOL stack and semiconductor substrate has a TSV cavity formed thereon. A conformal protective layer is disposed on the interior surface of the TSV cavity, along the BEOL stack and partway into the semiconductor substrate. The conformal protective layer serves to protect the dielectric layers within the BEOL stack during subsequent processing, improving the integrated circuit quality and product yield.
摘要翻译： 公开了一种改进的通硅通孔（TSV）。 半导体衬底具有在其上形成的后端（BEOL）叠层。 BEOL堆叠和半导体衬底在其上形成有TSV腔。 共形保护层沿着BEOL堆叠放置在TSV腔的内表面上，并且一部分设置在半导体衬底中。 共形保护层用于在后续处理期间保护BEOL堆叠内的电介质层，从而提高集成电路质量和产品产量。
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公开(公告)号：US20220123449A1
公开(公告)日：2022-04-21
申请号：US17076107
申请日：2020-10-21
摘要： Techniques regarding an embedded microstrip transmission line implemented in one more superconducting microwave electronic devices are provided. For example, one or more embodiments described herein can comprise an apparatus, which can include a superconducting material layer positioned on a raised portion of a dielectric substrate. The raised portion can extend from a surface of the dielectric substrate. The apparatus can also comprise a dielectric film that covers at least a portion of the superconducting material layer and the raised portion of the dielectric substrate.
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6.发明申请THROUGH-SILICON VIA STRUCTURE AND METHOD FOR IMPROVING BEOL DIELECTRIC PERFORMANCE 审中-公开通过硅的结构和提高BEOL介电性能的方法公开(公告)号：US20150069608A1
公开(公告)日：2015-03-12
申请号：US14023980
申请日：2013-09-11
发明人： Christopher Collins , Troy Lawrence Graves-Abe , Mukta G. Farooq , Tze-man Ko , William Francis Landers , Youbo Lin , Son Van Nguyen , Jennifer Ann Oakley , Deepika Priyadarshini
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L23/5226 , H01L21/76831 , H01L21/76898 , H01L23/528 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An improved through-silicon via (TSV) and method of fabrication are disclosed. A back-end-of-line (BEOL) stack is formed on a semiconductor substrate. A TSV cavity is formed in the BEOL stack and semiconductor substrate. A conformal protective layer is disposed on the interior surface of the TSV cavity, along the BEOL stack and partway into the semiconductor substrate. The conformal protective layer serves to protect the dielectric layers within the BEOL stack during subsequent processing, improving the integrated circuit quality and product yield.
摘要翻译： 公开了一种改进的通硅通孔（TSV）和制造方法。 在半导体衬底上形成后端（BEOL）堆叠。 在BEOL堆叠和半导体衬底中形成TSV腔。 共形保护层沿着BEOL堆叠放置在TSV腔的内表面上，并且一部分设置在半导体衬底中。 共形保护层用于在后续处理期间保护BEOL堆叠内的电介质层，从而提高集成电路质量和产品产量。
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公开(公告)号：US20220416392A1
公开(公告)日：2022-12-29
申请号：US17930269
申请日：2022-09-07
摘要： Techniques regarding an embedded microstrip transmission line implemented in one more superconducting microwave electronic devices are provided. For example, one or more embodiments described herein can comprise an apparatus, which can include a superconducting material layer positioned on a raised portion of a dielectric substrate. The raised portion can extend from a surface of the dielectric substrate. The apparatus can also comprise a dielectric film that covers at least a portion of the superconducting material layer and the raised portion of the dielectric substrate.
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公开(公告)号：US11469485B2
公开(公告)日：2022-10-11
申请号：US17076107
申请日：2020-10-21
摘要： Techniques regarding an embedded microstrip transmission line implemented in one more superconducting microwave electronic devices are provided. For example, one or more embodiments described herein can comprise an apparatus, which can include a superconducting material layer positioned on a raised portion of a dielectric substrate. The raised portion can extend from a surface of the dielectric substrate. The apparatus can also comprise a dielectric film that covers at least a portion of the superconducting material layer and the raised portion of the dielectric substrate.
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