公开(公告)号：US11043494B2

公开(公告)日：2021-06-22

申请号：US16460018

申请日：2019-07-02

申请人： International Business Machines Corporation

发明人： Lawrence A. Clevenger ,  Leigh Anne H. Clevenger ,  Mona A. Ebrish ,  Gauri Karve ,  Fee Li Lie ,  Deepika Priyadarshini ,  Indira Priyavarshini Seshadri ,  Nicole A. Saulnier

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L29/161 ,  H01L29/78 ,  H01L21/308 ,  H01L21/762 ,  H01L29/10

摘要： A method for fabricating fin field effect transistors comprises creating a pattern of self-aligned small cavities for P-type material growth using at least two hard mask layers, generating a pre-defined isolation area around each small cavity using a vertical spacer, selectively removing N-type material from the self-aligned small cavities, and growing P-type material in the small cavities. The P-type material may be silicon germanium (SiGe) and the N-type material may be tensile Silicon (t-Si). The pattern of self-aligned small cavities for P-type material growth is created by depositing two hard mask materials over a starting substrate wafer, selectively depositing photo resist over a plurality N-type areas, reactive ion etching to remove the second hard mask layer material over areas not covered by photo resist to create gaps in second hard mask layer, and removing the photo resist to expose the second hard mask material in the N-type areas.

公开(公告)号：US10366940B2

公开(公告)日：2019-07-30

申请号：US15835749

申请日：2017-12-08

申请人： International Business Machines Corporation

发明人： Griselda Bonilla ,  Elbert Huang ,  Son Nguyen ,  Takeshi Nogami ,  Christopher J. Penny ,  Deepika Priyadarshini

IPC分类号： H01L29/49 ,  H01L21/768 ,  H01L23/482 ,  H01L23/485 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8234

摘要： Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.

公开(公告)号：US10224283B2

公开(公告)日：2019-03-05

申请号：US15645668

申请日：2017-07-10

申请人： International Business Machines Corporation

发明人： Donald F. Canaperi ,  Son V. Nguyen ,  Takeshi Nogami ,  Deepika Priyadarshini

IPC分类号： H01L21/4763 ,  H01L23/532 ,  H01L21/768

摘要： A semiconductor device includes a metal-containing structure such as a copper-containing wire or plug and a composite capping layer formed over the metal-containing structure. The composite capping layer includes a manganese-containing layer disposed over the metal-containing structure, a silicon-containing low-k dielectric layer disposed over the manganese-containing layer, and an intermediate layer between the manganese-containing layer and the silicon-containing low-k dielectric layer. The intermediate layer is the reaction product of the manganese-containing layer and the silicon-containing low-k dielectric layer.

公开(公告)号：US09947622B2

公开(公告)日：2018-04-17

申请号：US15268012

申请日：2016-09-16

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Donald F. Canaperi ,  Daniel C. Edelstein ,  Alfred Grill ,  Son V. Nguyen ,  Takeshi Nogami ,  Deepika Priyadarshini ,  Hosadurga Shobha

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L29/872 ,  H01L29/739 ,  H01L21/285 ,  H01L23/528

CPC分类号： H01L23/53238 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76879 ,  H01L23/528 ,  H01L29/7395 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical device including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting electrical current. A liner is present between the opening and the copper including structure. The liner includes a superlattice structure comprised of a metal oxide layer, a metal layer present on the metal oxide layer, and a metal nitride layer that is present on the metal layer. A first layer of the superlattice structure that is in direct contact with the low-k dielectric material is one of said metal oxide layer and a final layer of the superlattice structure that is in direct contact with the copper including structure is one of the metal nitride layers.

公开(公告)号：US20180090588A1

公开(公告)日：2018-03-29

申请号：US15683322

申请日：2017-08-22

申请人： International Business Machines Corporation

发明人： Griselda Bonilla ,  Elbert Huang ,  Son Nguyen ,  Takeshi Nogami ,  Christopher J. Penny ,  Deepika Priyadarshini

IPC分类号： H01L29/49 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/786 ,  H01L29/423 ,  H01L21/768 ,  H01L29/66

CPC分类号： H01L23/4821 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/42392 ,  H01L29/4991 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

摘要： Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.

公开(公告)号：US20180090587A1

公开(公告)日：2018-03-29

申请号：US15683316

申请日：2017-08-22

申请人： International Business Machines Corporation

发明人： Griselda Bonilla ,  Elbert Huang ,  Son Nguyen ,  Takeshi Nogami ,  Christopher J. Penny ,  Deepika Priyadarshini

IPC分类号： H01L29/49 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/786 ,  H01L29/423 ,  H01L21/768 ,  H01L29/66

CPC分类号： H01L23/4821 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/42392 ,  H01L29/4991 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

摘要： Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.

公开(公告)号：US20170317032A1

公开(公告)日：2017-11-02

申请号：US15645668

申请日：2017-07-10

申请人： International Business Machines Corporation

发明人： Donald F. Canaperi ,  Son V. Nguyen ,  Takeshi Nogami ,  Deepika Priyadarshini

IPC分类号： H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76855

摘要： A semiconductor device includes a metal-containing structure such as a copper-containing wire or plug and a composite capping layer formed over the metal-containing structure. The composite capping layer includes a manganese-containing layer disposed over the metal-containing structure, a silicon-containing low-k dielectric layer disposed over the manganese-containing layer, and an intermediate layer between the manganese-containing layer and the silicon-containing low-k dielectric layer. The intermediate layer is the reaction product of the manganese-containing layer and the silicon-containing low-k dielectric layer.

公开(公告)号：US20170002469A1

公开(公告)日：2017-01-05

申请号：US15255694

申请日：2016-09-02

申请人： International Business Machines Corporation

发明人： Alfred Grill ,  Son V. Nguyen ,  Deepika Priyadarshini

IPC分类号： C23C16/52 ,  C23C16/34 ,  C23C16/515 ,  C23C16/48 ,  C23C16/511 ,  C23C16/27 ,  C23C16/452

CPC分类号： C23C16/52 ,  C23C16/14 ,  C23C16/274 ,  C23C16/34 ,  C23C16/452 ,  C23C16/45512 ,  C23C16/4558 ,  C23C16/482 ,  C23C16/511 ,  C23C16/515

摘要： A deposition apparatus for depositing a material on a substrate is provided. The deposition apparatus has a processing chamber defining a processing space in which the substrate is arranged, an ultraviolet radiation assembly configured to emit ultraviolet radiation and a microwave radiation assembly configured to emit microwave radiation into an excitation space that can be the same as the processing space, and a gas feed assembly configured to feed a precursor gas into the processing space and a reactive gas into the excitation space. The ultraviolet radiation assembly and the microwave radiation assembly are operated in combination to excite the reactive gas in the excitation space. The material is deposited on the substrate from the reaction of the excited reactive gas and the precursor gas. A method for using the deposition apparatus to deposit a material on a substrate is provided.

摘要翻译： 提供了一种用于在基板上沉积材料的沉积设备。 沉积装置具有限定其中布置基板的处理空间的处理室，被配置为发射紫外线辐射的紫外线辐射组件和被配置为将微波辐射发射到可以与处理空间相同的激发空间的微波辐射组件 以及气体供给组件，其构造成将前体气体进料到处理空间中，并将反应气体进料到激发空间中。 紫外线辐射组件和微波辐射组件联合操作以激发激发空间中的反应气体。 材料从被激发的反应气体和前体气体的反应沉积在衬底上。 提供了一种使用沉积设备将材料沉积在基底上的方法。

公开(公告)号：US20160314965A1

公开(公告)日：2016-10-27

申请号：US15152777

申请日：2016-05-12

申请人： International Business Machines Corporation

发明人： Son V. Nguyen ,  Deepika Priyadarshini

IPC分类号： H01L21/02 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L21/02326 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02296 ,  H01L21/0234 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/481 ,  H01L23/53295 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7843

摘要： Multilayer dielectric structures are provided with graded composition. For example, a multilayer dielectric structure includes a stack of dielectric films, wherein the dielectric films include at least a first SiCNO (silicon carbon nitride oxide) film and a second SiCNO film. The first SiCNO film has a first composition profile of C, N, and O atoms. The second SiCNO film has a second composition profile of C, N, and O atoms, which is different from the first composition profile of C, N, and O atoms. The composition profiles of C, N and/or O atoms of the constituent dielectric films of the multilayer dielectric structure are customized to enhance or otherwise optimize one or more electrical and/or physical properties of the multilayer dielectric structure.

摘要翻译： 多层电介质结构具有梯度组成。 例如，多层电介质结构包括一叠电介质膜，其中介电膜至少包括第一SiCNO（硅碳氮氧化物）膜和第二SiCNO膜。 第一种SiCNO膜具有C，N和O原子的第一组成分布。 第二SiCNO膜具有C，N和O原子的第二组成分布，其与C，N和O原子的第一组成分布不同。 定制多层电介质结构的构成电介质膜的C，N和/或O原子的组成分布，以增强或以其它方式优化多层电介质结构的一种或多种电和/或物理性质。

公开(公告)号：US08981466B2

公开(公告)日：2015-03-17

申请号：US13792374

申请日：2013-03-11

申请人： International Business Machines Corporation

发明人： Alfred Grill ,  Seth L. Knupp ,  Son V. Nguyen ,  Vamsi K. Paruchuri ,  Deepika Priyadarshini ,  Hosadurga K. Shobha

IPC分类号： H01L21/283 ,  H01L21/3115 ,  H01L21/473 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02247 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/0234 ,  H01L21/76283 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/481 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.