公开(公告)号：US20090002040A1

公开(公告)日：2009-01-01

申请号：US11964824

申请日：2007-12-27

申请人： Ic Su Oh ,  Kun Woo Park ,  Yong Ju Kim ,  Jong Woon Kim ,  Hee Wong Song ,  Hyung Soo Kim ,  Tae Jin Hwang

发明人： Ic Su Oh ,  Kun Woo Park ,  Yong Ju Kim ,  Jong Woon Kim ,  Hee Wong Song ,  Hyung Soo Kim ,  Tae Jin Hwang

IPC分类号： H03L7/06

CPC分类号： G11C7/22 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087

摘要： A DLL circuit for a semiconductor memory apparatus includes a delay line having a coarse delay chain, which has a plurality of coarse delayers connected in series and is inputted with a reference clock signal, and a plurality of fine delayers which receive output clock signals of the respective coarse delayers, and a delay control section for comparing phases of an output clock signal of a final coarse delayer among the coarse delayers with the reference clock signal and generating coarse control signals for controlling the coarse delayers and for comparing phases of an output clock signal of a fine delayer inputted with the output clock signals of the final coarse delayer, as a fine feedback clock signal, with the reference clock signal and generating fine control signals for controlling the fine delayers.

摘要翻译： 一种用于半导体存储装置的DLL电路包括具有粗略延迟链的延迟线，该延迟线具有串联连接并被输入参考时钟信号的多个粗延迟器，以及多个精细延迟器，其接收输出时钟信号的输出时钟信号 相应的粗延迟器和延迟控制部分，用于将粗延迟器中的最终粗延迟器的输出时钟信号的相位与参考时钟信号进行比较，并产生用于控制粗略延迟器的粗略控制信号，并用于比较输出时钟信号的相位 输入与最终粗略延迟器的输出时钟信号作为精细反馈时钟信号的精细延迟器与参考时钟信号，并产生用于控制精细延迟器的精细控制信号。

公开(公告)号：US07948287B2

公开(公告)日：2011-05-24

申请号：US11964824

申请日：2007-12-27

申请人： Ic Su Oh ,  Kun Woo Park ,  Yong Ju Kim ,  Jong Woon Kim ,  Hee Wong Song ,  Hyung Soo Kim ,  Tae Jin Hwang

发明人： Ic Su Oh ,  Kun Woo Park ,  Yong Ju Kim ,  Jong Woon Kim ,  Hee Wong Song ,  Hyung Soo Kim ,  Tae Jin Hwang

IPC分类号： H03L7/06

CPC分类号： G11C7/22 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087

摘要： A DLL circuit for a semiconductor memory apparatus includes a delay line having a coarse delay chain, which has a plurality of coarse delayers connected in series and is inputted with a reference clock signal, and a plurality of fine delayers which receive output clock signals of the respective coarse delayers, and a delay control section for comparing phases of an output clock signal of a final coarse delayer among the coarse delayers with the reference clock signal and generating coarse control signals for controlling the coarse delayers and for comparing phases of an output clock signal of a fine delayer inputted with the output clock signals of the final coarse delayer, as a fine feedback clock signal, with the reference clock signal and generating fine control signals for controlling the fine delayers.

摘要翻译： 一种用于半导体存储装置的DLL电路包括具有粗略延迟链的延迟线，该延迟线具有串联连接并被输入参考时钟信号的多个粗延迟器，以及多个精细延迟器，其接收输出时钟信号的输出时钟信号 相应的粗延迟器和延迟控制部分，用于将粗延迟器中的最终粗延迟器的输出时钟信号的相位与参考时钟信号进行比较，并产生用于控制粗略延迟器的粗略控制信号，并用于比较输出时钟信号的相位 输入与最终粗略延迟器的输出时钟信号作为精细反馈时钟信号的精细延迟器与参考时钟信号，并产生用于控制精细延迟器的精细控制信号。