Method of chemical-mechanical polishing and method of forming isolation layer using the same
    2.
    发明申请
    Method of chemical-mechanical polishing and method of forming isolation layer using the same 审中-公开
    化学机械抛光方法及使用其形成隔离层的方法

    公开(公告)号:US20080045018A1

    公开(公告)日:2008-02-21

    申请号:US11826899

    申请日:2007-07-19

    IPC分类号: H01L21/461

    CPC分类号: H01L21/31053 C09G1/02

    摘要: A method of chemical-mechanical polishing (CMP) and a method of forming an isolation layer using the same are provided. The method of chemical-mechanical polishing includes performing a first chemical-mechanical polishing operation on an insulating layer having a zeta potential with a first polarity by supplying a first slurry on the insulating layer, wherein the first slurry includes a first abrasive and ionic surfactants having a zeta potential with a second polarity opposite to the first polarity. The method of forming an isolation layer includes forming a mask layer on a substrate, etching the substrate to a desired depth using the mask layer such that a trench is formed in the substrate, forming the insulating layer on the substrate and performing the first chemical-mechanical polishing operation described above.

    摘要翻译: 提供化学机械抛光(CMP)的方法和使用其形成隔离层的方法。 化学机械抛光方法包括通过在绝缘层上提供第一浆料,对具有第一极性的ζ电位的绝缘层进行第一化学机械抛光操作,其中第一浆料包括第一磨料和离子表面活性剂,其具有 具有与第一极性相反的第二极性的ζ电位。 形成隔离层的方法包括在衬底上形成掩模层,使用掩模层将衬底蚀刻到所需的深度,使得在衬底中形成沟槽,在衬底上形成绝缘层,并执行第一化学 - 上述机械抛光操作。

    Semiconductor device having an insulating layer and method of fabricating the same
    3.
    发明申请
    Semiconductor device having an insulating layer and method of fabricating the same 审中-公开
    具有绝缘层的半导体器件及其制造方法

    公开(公告)号:US20070178644A1

    公开(公告)日:2007-08-02

    申请号:US11698070

    申请日:2007-01-26

    IPC分类号: H01L21/336

    摘要: A semiconductor device having a dielectric or an insulating layer with decreased (or minimal) erosion properties when performing metal Chemical Mechanical Polishing (CMP) and a method of fabricating the same are provided. The semiconductor device may include gate electrodes formed on a substrate. A first interlayer oxide layer may be formed on the substrate and between the gate electrodes. A second interlayer oxide layer, which is harder than the first interlayer oxide layer, may be formed on the first interlayer oxide layer. A plug electrode may be formed through the second interlayer oxide layer and the first interlayer oxide layer.

    摘要翻译: 提供了当执行金属化学机械抛光(CMP)时具有降低(或最小)腐蚀性能的电介质或绝缘层的半导体器件及其制造方法。 半导体器件可以包括形成在衬底上的栅电极。 第一层间氧化物层可以形成在衬底上和栅电极之间。 可以在第一层间氧化物层上形成比第一层间氧化物层硬的第二层间氧化物层。 可以通过第二层间氧化物层和第一层间氧化物层形成插塞电极。

    Method of Fabricating Semiconductor Device Having Dual Stress Liner
    4.
    发明申请
    Method of Fabricating Semiconductor Device Having Dual Stress Liner 审中-公开
    制造具有双重应力衬垫的半导体器件的方法

    公开(公告)号:US20080081406A1

    公开(公告)日:2008-04-03

    申请号:US11750491

    申请日:2007-05-18

    IPC分类号: H01L29/739

    摘要: A method of fabricating a semiconductor device comprising providing a substrate including a PMOS region and an NMOS region forming a PMOS gate electrode on the PMOS region and an NMOS gate electrode on the NMOS gate region, respectively, forming a stress liner on the PMOS region formed with the PMOS gate on the PMOS region and the NMOS region formed with the NMOS gate electrode on the NMOS region, and selectively applying radiation onto the stress liner formed on either one of the PMOS region and the NMOS region in an inert vapor ambiance.

    摘要翻译: 一种制造半导体器件的方法,包括在PMOS区上提供包括PMOS区和PMOS栅电极的NMOS区和在NMOS栅区上的NMOS栅电极的衬底,所述衬底在形成的PMOS区上形成应力衬垫 PMOS晶体管上的PMOS栅极和NMOS区域上形成有NMOS栅电极的NMOS区域,并以惰性蒸气气氛,选择性地将辐射施加到形成在PMOS区域和NMOS区域中的任一个上的应力衬垫上。