公开(公告)号：US20070128991A1

公开(公告)日：2007-06-07

申请号：US11634195

申请日：2006-12-06

申请人： Il-young Yoon ,  Hong-jae Shin ,  Se-young Lee ,  Jae-ouk Choo ,  Ja-eung Koo

发明人： Il-young Yoon ,  Hong-jae Shin ,  Se-young Lee ,  Jae-ouk Choo ,  Ja-eung Koo

IPC分类号： B24B1/00 ,  B24B29/00

CPC分类号： B24B37/245 ,  B24B37/26

摘要： A fixed abrasive polishing pad includes a base and a plurality of polishing layers on the base, wherein each polishing layer includes abrasive particles and apertures in a polishing surface of the polishing layer.

摘要翻译： 固定的研磨抛光垫包括基底和在基底上的多个抛光层，其中每个抛光层包括抛光层抛光表面中的研磨颗粒和孔。

公开(公告)号：US20070178644A1

公开(公告)日：2007-08-02

申请号：US11698070

申请日：2007-01-26

申请人： Ja-eung Koo ,  Il-young Yoon ,  Jae-ouk Choo ,  Yong-kuk Jeong ,  Seo-woo Nam ,  Hong-jae Shin

发明人： Ja-eung Koo ,  Il-young Yoon ,  Jae-ouk Choo ,  Yong-kuk Jeong ,  Seo-woo Nam ,  Hong-jae Shin

IPC分类号： H01L21/336

CPC分类号： H01L21/3212 ,  H01L21/76801 ,  H01L21/7684

摘要： A semiconductor device having a dielectric or an insulating layer with decreased (or minimal) erosion properties when performing metal Chemical Mechanical Polishing (CMP) and a method of fabricating the same are provided. The semiconductor device may include gate electrodes formed on a substrate. A first interlayer oxide layer may be formed on the substrate and between the gate electrodes. A second interlayer oxide layer, which is harder than the first interlayer oxide layer, may be formed on the first interlayer oxide layer. A plug electrode may be formed through the second interlayer oxide layer and the first interlayer oxide layer.

摘要翻译： 提供了当执行金属化学机械抛光（CMP）时具有降低（或最小）腐蚀性能的电介质或绝缘层的半导体器件及其制造方法。 半导体器件可以包括形成在衬底上的栅电极。 第一层间氧化物层可以形成在衬底上和栅电极之间。 可以在第一层间氧化物层上形成比第一层间氧化物层硬的第二层间氧化物层。 可以通过第二层间氧化物层和第一层间氧化物层形成插塞电极。

公开(公告)号：US07785951B2

公开(公告)日：2010-08-31

申请号：US11831223

申请日：2007-07-31

申请人： Seo-woo Nam ,  Il-young Yoon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Il-young Yoon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L21/8238

CPC分类号： H01L29/7843 ,  H01L21/31053 ,  H01L21/3185 ,  H01L21/823807

摘要： Methods of forming integrated circuit devices include forming first, second and third gate electrodes on a semiconductor substrate. A first stress film is provided that covers the first gate electrode and at least a first portion of the third gate electrode. The first stress film has a sufficiently high internal stress characteristic to impart a net compressive stress in a first portion of the semiconductor substrate extending opposite the first gate electrode. A second stress film is also provided. The second stress film covers the second gate electrode and at least a second portion of the third gate electrode. The second stress film has a sufficiently high internal stress characteristic to impart a net tensile stress in a second portion of the semiconductor substrate extending opposite the second gate electrode. The second stress film has an upper surface that is coplanar with an upper surface of the first stress film at a location adjacent the third gate electrode.

摘要翻译： 形成集成电路器件的方法包括在半导体衬底上形成第一，第二和第三栅电极。 提供了覆盖第一栅电极和第三栅电极的至少第一部分的第一应力膜。 第一应力膜具有足够高的内部应力特性，以在与第一栅电极相对延伸的半导体衬底的第一部分中赋予净压应力。 还提供了第二应力膜。 第二应力膜覆盖第二栅电极和第三栅电极的至少第二部分。 第二应力膜具有足够高的内部应力特性，以在与第二栅电极相对延伸的半导体衬底的第二部分中施加净拉伸应力。 第二应力膜具有在与第三栅电极相邻的位置处与第一应力膜的上表面共面的上表面。

公开(公告)号：US20080081476A1

公开(公告)日：2008-04-03

申请号：US11831223

申请日：2007-07-31

申请人： Seo-woo Nam ,  Il-young Yoon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Il-young Yoon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L21/302 ,  H01L21/31

CPC分类号： H01L29/7843 ,  H01L21/31053 ,  H01L21/3185 ,  H01L21/823807

摘要： Methods of forming integrated circuit devices include forming first, second and third gate electrodes on a semiconductor substrate. A first stress film is provided that covers the first gate electrode and at least a first portion of the third gate electrode. The first stress film has a sufficiently high internal stress characteristic to impart a net compressive stress in a first portion of the semiconductor substrate extending opposite the first gate electrode. A second stress film is also provided. The second stress film covers the second gate electrode and at least a second portion of the third gate electrode. The second stress film has a sufficiently high internal stress characteristic to impart a net tensile stress in a second portion of the semiconductor substrate extending opposite the second gate electrode. The second stress film has an upper surface that is coplanar with an upper surface of the first stress film at a location adjacent the third gate electrode.

摘要翻译： 形成集成电路器件的方法包括在半导体衬底上形成第一，第二和第三栅电极。 提供了覆盖第一栅电极和第三栅电极的至少第一部分的第一应力膜。 第一应力膜具有足够高的内部应力特性，以在与第一栅电极相对延伸的半导体衬底的第一部分中赋予净压应力。 还提供了第二应力膜。 第二应力膜覆盖第二栅电极和第三栅电极的至少第二部分。 第二应力膜具有足够高的内部应力特性，以在与第二栅电极相对延伸的半导体衬底的第二部分中施加净拉伸应力。 第二应力膜具有在与第三栅电极相邻的位置处与第一应力膜的上表面共面的上表面。

公开(公告)号：US20100065919A1

公开(公告)日：2010-03-18

申请号：US12621079

申请日：2009-11-18

申请人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L27/092

CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.

摘要翻译： 半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅极电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和 第二晶体管区域并具有第三栅电极。 第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。 第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。 与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。 还描述了相关方法。

公开(公告)号：US07642148B2

公开(公告)日：2010-01-05

申请号：US11851500

申请日：2007-09-07

申请人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L21/8238

CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.

摘要翻译： 半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅极电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和 第二晶体管区域并具有第三栅电极。 第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。 第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。 与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。 还描述了相关方法。

公开(公告)号：US07902609B2

公开(公告)日：2011-03-08

申请号：US12621079

申请日：2009-11-18

申请人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L23/62

CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.

摘要翻译： 半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和 第二晶体管区域并具有第三栅电极。 第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。 第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。 与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。 还描述了相关方法。

公开(公告)号：US20090280637A1

公开(公告)日：2009-11-12

申请号：US12453326

申请日：2009-05-07

申请人： Kyoung-woo Lee ,  Hong-jae Shin ,  Jae-hak Kim ,  Jae-ouk Choo

发明人： Kyoung-woo Lee ,  Hong-jae Shin ,  Jae-hak Kim ,  Jae-ouk Choo

IPC分类号： H01L21/768

CPC分类号： H01L21/7682 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02362 ,  H01L21/31695

摘要： Provided is a method of manufacturing a semiconductor device. The method employs multi-step removal on a plurality of different porogens included in a low dielectric layer both before and after metal lines are formed, thereby facilitating formation of an ultra low dielectric constant layer which is used as an insulation layer between metal lines of a semiconductor device. The method may include forming an interlayer dielectric layer on a substrate, forming a plurality of porogens in the interlayer dielectric layer, removing a portion of the plurality of porogens in the interlayer dielectric layer to form a plurality of first pores in the interlayer dielectric layer, forming a wiring pattern where the plurality of first pores are formed, and removing the remaining porogens of the plurality of porogens to form a plurality of second pores in the interlayer dielectric layer.

摘要翻译： 提供一种制造半导体器件的方法。 该方法在形成金属线之前和之后，在包含在低电介质层中的多个不同的致孔剂上采用多步除去，从而有助于形成超低介电常数层，该超低介电常数层用作金属线之间的绝缘层 半导体器件。 该方法可以包括在衬底上形成层间电介质层，在层间电介质层中形成多个致孔剂，去除层间电介质层中的多个致孔剂的一部分，以在层间电介质层中形成多个第一孔， 形成其中形成有多个第一孔的布线图案，并且除去多个致孔剂中剩余的孔隙原，以在层间电介质层中形成多个第二孔。

公开(公告)号：US20080079087A1

公开(公告)日：2008-04-03

申请号：US11851500

申请日：2007-09-07

申请人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.

摘要翻译： 半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅极电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和 第二晶体管区域并具有第三栅电极。 第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。 第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。 与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。 还描述了相关方法。

公开(公告)号：US07687915B2

公开(公告)日：2010-03-30

申请号：US12216097

申请日：2008-06-30

申请人： Kyoung-woo Lee ,  Hong-jae Shin

发明人： Kyoung-woo Lee ,  Hong-jae Shin

IPC分类号： H01L23/522

CPC分类号： H01L23/585 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： Example embodiments relate to semiconductor devices having a single body crack stop structure configured to reduce or prevent crack propagation and/or moisture penetration. A semiconductor substrate according to example embodiments may include an active region and a crack stop region surrounding the active region. Interlayer insulating layers may be sequentially stacked on the semiconductor substrate. The interlayer insulating layers may include first dual damascene patterns and a first opening. The first dual damascene patterns may be formed in the interlayer insulating layers so as to be perpendicular to the surface of the semiconductor substrate while exposing a first portion of the semiconductor substrate. The first opening may be formed in the crack stop region and may extend through the interlayer insulating layers to expose a second portion of the semiconductor substrate. First dual damascene metal wirings may be formed in the first dual damascene patterns and may contact the exposed first portion of the semiconductor substrate. A single body first crack stop structure may be formed in the first opening so as to contact the exposed second portion of the semiconductor substrate.

摘要翻译： 示例实施例涉及具有单体裂纹停止结构的半导体器件，其被配置为减少或防止裂纹扩展和/或湿气穿透。 根据示例性实施例的半导体衬底可以包括有源区和围绕有源区的裂纹停止区。 层间绝缘层可以顺序堆叠在半导体衬底上。 层间绝缘层可以包括第一双镶嵌图案和第一开口。 可以在层间绝缘层中形成第一双镶嵌图案，以便在暴露半导体基板的第一部分的同时垂直于半导体基板的表面。 第一开口可以形成在裂纹停止区域中并且可以延伸穿过层间绝缘层以暴露半导体衬底的第二部分。 第一双镶嵌金属布线可以形成在第一双镶嵌图案中并且可以接触半导体基板的暴露的第一部分。 可以在第一开口中形成单体第一裂纹阻挡结构，以与半导体衬底的暴露的第二部分接触。