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1.发明授权Innovative method to build a high precision analog capacitor with low voltage coefficient and hysteresis 有权建立低电压系数和滞后的高精度模拟电容的创新方法公开(公告)号：US06706635B2
公开(公告)日：2004-03-16
申请号：US10163450
申请日：2002-06-05
申请人： Imran M. Khan , William E. Nehrer , James Todd , Weidong Tian , Louis N. Hutter
发明人： Imran M. Khan , William E. Nehrer , James Todd , Weidong Tian , Louis N. Hutter
IPC分类号： H01L21302
CPC分类号： H01L28/60 , H01L21/3212 , H01L21/76838 , H01L27/0805
摘要： The present invention relates to a method for forming an anlog capacitor on a semiconductor substrate. The method comprises forming a field oxide over a portion of the substrate, and forming a polysilicon layer over the field oxide layer, and subsequently forming a silicide over the polysilicon layer. A first interlayer dielectric layer is formed over the substrate, and a capacitor masking pattern is formed. The first interlayer dielectric is etched using the capacitor masking pattern as a mask and the silicide layer as an etch stop, and a thin dielectric is formed over the substrate. A contact masking pattern is formed over the substrate, and a subsequent etch is performed on the thin dielectric and the first interlayer dielectric using the silicide and substrate as an etch stop. A metal layer is deposited over the substrate, and is subsequently planarized, thereby defining an analog capacitor.
摘要翻译： 本发明涉及一种在半导体衬底上形成anlog电容器的方法。 该方法包括在衬底的一部分上形成场氧化物，并在场氧化物层上形成多晶硅层，随后在多晶硅层上形成硅化物。 在衬底上形成第一层间电介质层，形成电容器屏蔽图案。 使用电容器掩模图案作为掩模蚀刻第一层间电介质，并且将硅化物层作为蚀刻停止层，并在衬底上形成薄的电介质。 在衬底上形成接触掩模图案，并且使用硅化物和衬底作为蚀刻停止层，在薄电介质和第一层间电介质上进行随后的蚀刻。 金属层沉积在衬底上，随后被平坦化，从而限定模拟电容器。
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2.发明授权公开(公告)号：US06979615B2
公开(公告)日：2005-12-27
申请号：US10243405
申请日：2002-09-12
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L21/8242
CPC分类号： H01L29/66825 , H01L21/28273
摘要： A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate. A PSG layer is disposed outwardly from the polysilicon layer and planarized. The device is pattern etched to form a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer. A dielectric layer is formed in the capacitor channel disposed outwardly from the polysilicon layer. A tungsten plug operable to substantially fill the capacitor channel is formed.
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公开(公告)号：US07279738B2
公开(公告)日：2007-10-09
申请号：US11145460
申请日：2005-06-02
IPC分类号： H01L29/788
CPC分类号： H01L29/66825 , H01L21/28273
摘要： A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate. A PSG layer is disposed outwardly from the polysilicon layer and planarized. The device is pattern etched to form a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer. A dielectric layer is formed in the capacitor channel disposed outwardly from the polysilicon layer. A tungsten plug operable to substantially fill the capacitor channel is formed.
摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成氧化物层。 多晶硅层从氧化物层向外设置，其中多晶硅层形成浮栅。 PSG层从多晶硅层向外设置并平坦化。 该器件被图形蚀刻以形成电容器通道，其中电容器通道基本上设置在由多晶硅层形成的浮置栅极的上方。 在从多晶硅层向外设置的电容器通道中形成介电层。 形成可操作以充分充电电容器通道的钨插头。
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