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    Innovative method to build a high precision analog capacitor with low voltage coefficient and hysteresis
    1.
    发明授权
    Innovative method to build a high precision analog capacitor with low voltage coefficient and hysteresis 有权
    建立低电压系数和滞后的高精度模拟电容的创新方法

    公开(公告)号：US06706635B2

    公开(公告)日：2004-03-16

    申请号：US10163450

    申请日：2002-06-05

    申请人： Imran M. Khan ,  William E. Nehrer ,  James Todd ,  Weidong Tian ,  Louis N. Hutter

    发明人： Imran M. Khan ,  William E. Nehrer ,  James Todd ,  Weidong Tian ,  Louis N. Hutter

    IPC分类号： H01L21302

    CPC分类号： H01L28/60 ,  H01L21/3212 ,  H01L21/76838 ,  H01L27/0805

    摘要： The present invention relates to a method for forming an anlog capacitor on a semiconductor substrate. The method comprises forming a field oxide over a portion of the substrate, and forming a polysilicon layer over the field oxide layer, and subsequently forming a silicide over the polysilicon layer. A first interlayer dielectric layer is formed over the substrate, and a capacitor masking pattern is formed. The first interlayer dielectric is etched using the capacitor masking pattern as a mask and the silicide layer as an etch stop, and a thin dielectric is formed over the substrate. A contact masking pattern is formed over the substrate, and a subsequent etch is performed on the thin dielectric and the first interlayer dielectric using the silicide and substrate as an etch stop. A metal layer is deposited over the substrate, and is subsequently planarized, thereby defining an analog capacitor.

    摘要翻译： 本发明涉及一种在半导体衬底上形成anlog电容器的方法。 该方法包括在衬底的一部分上形成场氧化物，并在场氧化物层上形成多晶硅层，随后在多晶硅层上形成硅化物。 在衬底上形成第一层间电介质层，形成电容器屏蔽图案。 使用电容器掩模图案作为掩模蚀刻第一层间电介质，并且将硅化物层作为蚀刻停止层，并在衬底上形成薄的电介质。 在衬底上形成接触掩模图案，并且使用硅化物和衬底作为蚀刻停止层，在薄电介质和第一层间电介质上进行随后的蚀刻。 金属层沉积在衬底上，随后被平坦化，从而限定模拟电容器。

    Zero temperature coefficient capacitor
    3.
    发明授权
    Zero temperature coefficient capacitor 有权
    零温度系数电容

    公开(公告)号：US08373215B2

    公开(公告)日：2013-02-12

    申请号：US13267674

    申请日：2011-10-06

    申请人： Weidong Tian ,  Imran Khan

    发明人： Weidong Tian ,  Imran Khan

    IPC分类号： H01L29/92

    CPC分类号： H01L28/40 ,  H01L27/0629 ,  H01L29/94

    摘要： A zero temperature coefficient (ZTC) capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7×1020 atoms/cm3 and 2.3×1020 atoms/cm3. An integrated circuit containing a ZTC capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7×1020 atoms/cm3 and 2.3×1020 atoms/cm3. A process of forming an integrated circuit containing a ZTC capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7×1020 atoms/cm3 and 2.3×1020 atoms/cm3.

    摘要翻译： 零温度系数（ZTC）电容器，其包括磷密度在1.7×1020原子/ cm3至2.3×1020原子/ cm3之间的二氧化硅介电层。 一种包含ZTC电容器的集成电路，其包括磷密度为1.7×1020原子/ cm3至2.3×1020原子/ cm3的二氧化硅电介质层。 形成包含Zinc电容器的集成电路的过程，该电容器包括磷密度为1.7×1020原子/ cm3至2.3×1020原子/ cm3的二氧化硅介电层。

    Versatile system for charge dissipation in the formation of semiconductor device structures
    5.
    发明授权
    Versatile system for charge dissipation in the formation of semiconductor device structures 有权
    用于形成半导体器件结构的电荷耗散的通用系统

    公开(公告)号：US07119444B2

    公开(公告)日：2006-10-10

    申请号：US10917763

    申请日：2004-08-13

    申请人： Weidong Tian ,  Bradley Sucher ,  Zafar Imam

    发明人： Weidong Tian ,  Bradley Sucher ,  Zafar Imam

    IPC分类号： H01L23/48

    CPC分类号： H01L27/0248 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200), obviating overstress or break down damage to a focal device structure (208) that might result from uncontrolled dissipation of the aberrant charge. A substrate (202) has first and second intermediate structures (204, 206) disposed atop the substrate, with the focal structure disposed atop the substrate therebetween. A first conductive structure (210) is disposed atop the second intermediate structure, the focal structure, and a portion of the first intermediate structure. A third intermediate structure (214) is disposed contiguously atop the first conductive structure and the first intermediate layer. A void (216) is formed in a peripheral region (218) of device segment, through the first and third intermediate layers down to the substrate. A second conductive structure (220) is disposed atop the third intermediate structure such that it couples the substrate through the void.

    摘要翻译： 本发明提供了一种用于消散在制造半导体器件段（200）期间可能累积的任何异常电荷的系统，消除过应力或分解对可能由于异常电荷的不受控耗散而导致的焦点设备结构（208）的损坏 。 衬底（202）具有设置在衬底顶部的第一和第二中间结构（204,206），其中焦点结构设置在衬底之上。 第一导电结构（210）设置在第二中间结构，焦点结构和第一中间结构的一部分的顶部。 第三中间结构（214）在第一导电结构和第一中间层的上方相邻地设置。 在器件段的周边区域（218）中通过第一和第三中间层向下形成空隙（216）。 第二导电结构（220）设置在第三中间结构的顶部，使得其通过空隙连接衬底。

    Semiconductor device including a dielectric layer having a gettering material located therein and a method of manufacture therefor
    6.
    发明授权
    Semiconductor device including a dielectric layer having a gettering material located therein and a method of manufacture therefor 有权
    包括其中具有吸气材料的电介质层的半导体器件及其制造方法

    公开(公告)号：US07045418B2

    公开(公告)日：2006-05-16

    申请号：US10387164

    申请日：2003-03-12

    申请人： Jozef Mitros ,  Weidong Tian ,  Pinghai Hao ,  Victor Ivanov

    发明人： Jozef Mitros ,  Weidong Tian ,  Pinghai Hao ,  Victor Ivanov

    IPC分类号： H01L21/336 ,  H01L29/76

    CPC分类号： H01L27/11526 ,  H01L21/28194 ,  H01L27/115 ,  H01L27/11534 ,  H01L29/511 ,  H01L29/66825 ,  Y10S257/913

    摘要： The present invention provides a semiconductor device (200), a method of manufacture therefor and an integrated circuit including the same. In one embodiment of the invention, the semiconductor device (200) includes a floating gate (230) located over a semiconductor substrate (210), wherein the floating gate (230) has a metal control gate (250) located thereover. The semiconductor device (200), in the same embodiment, further includes a dielectric layer (240) located between the floating gate 230 and the metal control gate (250), the dielectric layer (240) having a gettering material located therein.

    摘要翻译： 本发明提供一种半导体器件（200）及其制造方法以及包括该半导体器件的集成电路。 在本发明的一个实施例中，半导体器件（200）包括位于半导体衬底（210）上的浮动栅极（230），其中浮置栅极（230）具有位于其上的金属控制栅极（250）。 在同一实施例中，半导体器件（200）还包括位于浮置栅极230和金属控制栅极（250）之间的介电层（240），介电层（240）具有位于其中的吸气材料。

    On current in one-time-programmable memory cells
    8.
    发明授权
    On current in one-time-programmable memory cells 有权
    关于一次可编程存储单元中的电流

    公开(公告)号：US08679929B2

    公开(公告)日：2014-03-25

    申请号：US13312304

    申请日：2011-12-06

    申请人： Shanjen “Robert” Pan ,  Allan T. Mitchell ,  Weidong Tian

    发明人： Shanjen “Robert” Pan ,  Allan T. Mitchell ,  Weidong Tian

    IPC分类号： H01L21/336 ,  H01L21/425

    CPC分类号： H01L21/28273 ,  H01L27/11206 ,  H01L27/11233 ,  H01L29/66825 ,  H01L29/7885

    摘要： A method of fabricating a one-time programmable (OTP) memory cell with improved read current in one of its programmed states, and a memory cell so fabricated. The OTP memory cell is constructed with trench isolation structures on its sides. After trench etch, and prior to filling the isolation trenches with dielectric material, a fluorine implant is performed into the trench surfaces. The implant may be normal to the device surface or at an angle from the normal. Completion of the cell transistor to form a floating-gate metal-oxide-semiconductor (MOS) transistor is then carried out. Improved on-state current (Ion) results from the fluorine implant.

    摘要翻译： 一种在其编程状态之一制造具有改进的读取电流的一次性可编程（OTP）存储单元的方法，以及如此制造的存储单元。 OTP存储单元的侧面由沟槽隔离结构构成。 在沟槽蚀刻之后，并且在用介电材料填充隔离沟槽之前，在沟槽表面中执行氟注入。 植入物可能垂直于装置表面或与法线成一角度。 然后完成单元晶体管以形成浮栅金属氧化物半导体（MOS）晶体管。 来自氟植入物的改进的导通电流（Ion）。

    On Current in One-Time-Programmable Memory Cells
    9.
    发明申请
    On Current in One-Time-Programmable Memory Cells 有权
    关于一次性可编程存储器单元中的电流

    公开(公告)号：US20130143375A1

    公开(公告)日：2013-06-06

    申请号：US13312304

    申请日：2011-12-06

    申请人： Shanjen "Robert" Pan ,  Allan T. Mitchell ,  Weidong Tian

    发明人： Shanjen "Robert" Pan ,  Allan T. Mitchell ,  Weidong Tian

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28273 ,  H01L27/11206 ,  H01L27/11233 ,  H01L29/66825 ,  H01L29/7885

    摘要： A method of fabricating a one-time programmable (OTP) memory cell with improved read current in one of its programmed states, and a memory cell so fabricated. The OTP memory cell is constructed with trench isolation structures on its sides. After trench etch, and prior to filling the isolation trenches with dielectric material, a fluorine implant is performed into the trench surfaces. The implant may be normal to the device surface or at an angle from the normal. Completion of the cell transistor to form a floating-gate metal-oxide-semiconductor (MOS) transistor is then carried out. Improved on-state current (Ion) results from the fluorine implant.

    摘要翻译： 一种在其编程状态之一制造具有改进的读取电流的一次可编程（OTP）存储单元的方法，以及如此制造的存储器单元。 OTP存储单元的侧面由沟槽隔离结构构成。 在沟槽蚀刻之后，并且在用介电材料填充隔离沟槽之前，在沟槽表面中执行氟注入。 植入物可能垂直于装置表面或与法线成一角度。 然后完成单元晶体管以形成浮栅金属氧化物半导体（MOS）晶体管。 来自氟植入物的改进的导通电流（Ion）。

    VERSATILE SYSTEM FOR CHARGE DISSIPATION IN THE FORMATION OF SEMICONDUCTOR DEVICE STRUCTURES
    10.
    发明申请
    VERSATILE SYSTEM FOR CHARGE DISSIPATION IN THE FORMATION OF SEMICONDUCTOR DEVICE STRUCTURES 有权
    用于形成半导体器件结构的充电放电的多元系统

    公开(公告)号：US20070057247A1

    公开(公告)日：2007-03-15

    申请号：US11468648

    申请日：2006-08-30

    申请人： Weidong Tian ,  Bradley Sucher ,  Zafar Imam

    发明人： Weidong Tian ,  Bradley Sucher ,  Zafar Imam

    IPC分类号： H01L31/00

    CPC分类号： H01L27/0248 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200), obviating overstress or break down damage to a focal device structure (208) that might result from uncontrolled dissipation of the aberrant charge. A substrate (202) has first and second intermediate structures (204, 206) disposed atop the substrate, with the focal structure disposed atop the substrate therebetween. A first conductive structure (210) is disposed atop the second intermediate structure, the focal structure, and a portion of the first intermediate structure. A third intermediate structure (214) is disposed contiguously atop the first conductive structure and the first intermediate layer. A void (216) is formed in a peripheral region (218) of device segment, through the first and third intermediate layers down to the substrate. A second conductive structure (220) is disposed atop the third intermediate structure such that it couples the substrate through the void.

    摘要翻译： 本发明提供了一种用于消散在制造半导体器件段（200）期间可能累积的任何异常电荷的系统，消除过应力或分解对可能由于异常电荷的不受控耗散而导致的焦点设备结构（208）的损坏 。 衬底（202）具有设置在衬底顶部的第一和第二中间结构（204,206），其中焦点结构设置在衬底之上。 第一导电结构（210）设置在第二中间结构，焦点结构和第一中间结构的一部分的顶部。 第三中间结构（214）在第一导电结构和第一中间层的上方相邻地设置。 在器件段的周边区域（218）中通过第一和第三中间层向下形成空隙（216）。 第二导电结构（220）设置在第三中间结构的顶部，使得其通过空隙连接衬底。