公开(公告)号：US20050186734A1

公开(公告)日：2005-08-25

申请号：US10786239

申请日：2004-02-24

申请人： In-Wook Cho ,  Nae-In Lee ,  Kwang-Wook Koh ,  Geun-Jong Bae ,  Sang-Su Kim ,  Jin-Hee Kim ,  Sung-Ho Kim ,  Ki-Chul Kim

发明人： In-Wook Cho ,  Nae-In Lee ,  Kwang-Wook Koh ,  Geun-Jong Bae ,  Sang-Su Kim ,  Jin-Hee Kim ,  Sung-Ho Kim ,  Ki-Chul Kim

IPC分类号： H01L27/10 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/115 ,  H01L27/11568 ,  Y10S438/954

摘要： A method of manufacturing a non-volatile semiconductor memory device begins by forming a dielectric layer pattern having an ONO composition on a substrate. A polysilicon layer is formed on the substrate including over the dielectric layer pattern. The polysilicon layer is patterned to form a split polysilicon layer pattern that exposes part of the dielectric layer pattern. The exposed dielectric layer is etched, and then impurities are implanted into portions of the substrate using the split polysilicon layer pattern as a mask to thereby form a source region having a vertical profile in the substrate.

摘要翻译： 制造非易失性半导体存储器件的方法是通过在衬底上形成具有ONO组成的电介质层图案而开始的。 在包括在电介质层图案上的衬底上形成多晶硅层。 图案化多晶硅层以形成暴露部分介电层图案的分裂多晶硅层图案。 暴露的电介质层被蚀刻，然后使用分离多晶硅层图案作为掩模将杂质注入到衬底的部分中，从而在衬底中形成具有垂直轮廓的源区。

公开(公告)号：US06998309B2

公开(公告)日：2006-02-14

申请号：US10786239

申请日：2004-02-24

申请人： In-Wook Cho ,  Nae-In Lee ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Sang-Su Kim ,  Jin-Hee Kim ,  Sung-Ho Kim ,  Ki-Chul Kim

发明人： In-Wook Cho ,  Nae-In Lee ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Sang-Su Kim ,  Jin-Hee Kim ,  Sung-Ho Kim ,  Ki-Chul Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568 ,  Y10S438/954

摘要： A method of manufacturing a non-volatile semiconductor memory device begins by forming a dielectric layer pattern having an ONO composition on a substrate. A polysilicon layer is formed on the substrate including over the dielectric layer pattern. The polysilicon layer is patterned to form a split polysilicon layer pattern that exposes part of the dielectric layer pattern. The exposed dielectric layer is etched, and then impurities are implanted into portions of the substrate using the split polysilicon layer pattern as a mask to thereby form a source region having a vertical profile in the substrate.

摘要翻译： 制造非易失性半导体存储器件的方法是通过在衬底上形成具有ONO组成的电介质层图案而开始的。 在包括在电介质层图案上的衬底上形成多晶硅层。 图案化多晶硅层以形成暴露部分介电层图案的分裂多晶硅层图案。 暴露的电介质层被蚀刻，然后使用分离多晶硅层图案作为掩模将杂质注入到衬底的部分中，从而在衬底中形成具有垂直轮廓的源区。

公开(公告)号：US07060563B2

公开(公告)日：2006-06-13

申请号：US10953553

申请日：2004-09-30

申请人： Geum-Jong Bae ,  Nae-In Lee ,  Sang Su Kim ,  Ki Chul Kim ,  Jin-Hee Kim ,  In-Wook Cho ,  Sung-Ho Kim ,  Kwang-Wook Koh

发明人： Geum-Jong Bae ,  Nae-In Lee ,  Sang Su Kim ,  Ki Chul Kim ,  Jin-Hee Kim ,  In-Wook Cho ,  Sung-Ho Kim ,  Kwang-Wook Koh

IPC分类号： H01L21/8247

CPC分类号： H01L29/792 ,  H01L29/7923 ,  Y10S438/954

摘要： A local SONOS structure having a two-piece gate and a self-aligned ONO structure includes: a substrate; an ONO structure on the substrate; a first gate layer on and aligned with the ONO structure; a gate insulator on the substrate aside the ONO structure; and a second gate layer on the first gate layer and on the gate insulator. The first and second gate layers are electrically connected together. Together, the ONO structure and first and second gate layers define at least a 1-bit local SONOS structure. A corresponding method of manufacture includes: providing a substrate; forming an ONO structure on the substrate; forming a first gate layer on and aligned with the ONO structure; forming a gate insulator on the substrate aside the ONO structure; forming a second gate layer on the first gate layer and on the gate insulator; and electrically connecting the first and second gate layers.

摘要翻译： 具有两件式门和自对准ONO结构的本地SONOS结构包括：衬底; 基底上的ONO结构; 在ONO结构上并与ONO结构对准的第一栅极层; 衬底上的栅极绝缘体旁边的ONO结构; 以及在第一栅极层上和栅极绝缘体上的第二栅极层。 第一和第二栅极层电连接在一起。 ONO结构和第一和第二栅极层一起定义至少1位本地SONOS结构。 相应的制造方法包括：提供衬底; 在基板上形成ONO结构; 在ONO结构上形成第一栅极层并与其结合; 在衬底上形成栅极绝缘体，除了ONO结构; 在第一栅极层和栅极绝缘体上形成第二栅极层; 并且电连接第一和第二栅极层。

公开(公告)号：US06815764B2

公开(公告)日：2004-11-09

申请号：US10388631

申请日：2003-03-17

申请人： Geum-Jong Bae ,  Nae-In Lee ,  Sang Su Kim ,  Ki Chul Kim ,  Jin-Hee Kim ,  In-Wook Cho ,  Sung-Ho Kim ,  Kwang-Wook Koh

发明人： Geum-Jong Bae ,  Nae-In Lee ,  Sang Su Kim ,  Ki Chul Kim ,  Jin-Hee Kim ,  In-Wook Cho ,  Sung-Ho Kim ,  Kwang-Wook Koh

IPC分类号： H01L29792

CPC分类号： H01L29/792 ,  H01L29/7923 ,  Y10S438/954

摘要： A local SONOS structure having a two-piece gate and a self-aligned ONO structure includes: a substrate; an ONO structure on the substrate; a first gate layer on and aligned with the ONO structure; a gate insulator on the substrate aside the ONO structure; and a second gate layer on the first gate layer and on the gate insulator. The first and second gate layers are electrically connected together. Together, the ONO structure and first and second gate layers define at least a 1-bit local SONOS structure. A corresponding method of manufacture includes: providing a substrate; forming an ONO structure on the substrate; forming a first gate layer on and aligned with the ONO structure; forming a gate insulator on the substrate aside the ONO structure; forming a second gate layer on the first gate layer and on the gate insulator; and electrically connecting the first and second gate layers.

摘要翻译： 具有两件式门和自对准ONO结构的本地SONOS结构包括：衬底; 基底上的ONO结构; 在ONO结构上并与ONO结构对准的第一栅极层; 衬底上的栅极绝缘体旁边的ONO结构; 以及在第一栅极层上和栅极绝缘体上的第二栅极层。 第一和第二栅极层电连接在一起。 ONO结构和第一和第二栅极层一起定义至少1位本地SONOS结构。 相应的制造方法包括：提供衬底; 在基板上形成ONO结构; 在ONO结构上形成第一栅极层并与其结合; 在衬底上形成栅极绝缘体，除了ONO结构; 在第一栅极层和栅极绝缘体上形成第二栅极层; 并且电连接第一和第二栅极层。

公开(公告)号：US20060208303A1

公开(公告)日：2006-09-21

申请号：US11378505

申请日：2006-03-17

申请人： Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

发明人： Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

IPC分类号： H01L29/76

CPC分类号： H01L27/11568 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

摘要： The present invention discloses a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same. The method includes providing a semiconductor substrate having a nonvolatile memory region, a first region, and a second region. A triple layer composed of a tunnel oxide layer, a charge storing layer and a first deposited oxide layer on the semiconductor substrate is formed sequentially. The triple layer on the semiconductor substrate except the nonvolatile memory region is then removed. A second deposited oxide layer is formed on an entire surface of the semiconductor substrate including the first and second regions from which the triple layer is removed. The second deposited oxide layer on the second region is removed, and a first thermal oxide layer is formed on the entire surface of the semiconductor substrate including the second region from which the second deposited oxide layer is removed. The semiconductor device can be manufactured according to the present invention to have a reduced processing time and a reduced change of impurity doping profile. The thickness of a blocking oxide layer and a high voltage gate oxide layer can be controlled.

摘要翻译： 本发明公开了一种具有浮动阱式非易失性存储单元的半导体器件及其制造方法。 该方法包括提供具有非易失性存储区域，第一区域和第二区域的半导体衬底。 顺序地形成由半导体衬底上的隧道氧化物层，电荷存储层和第一沉积氧化物层组成的三层。 然后除去非易失性存储区域之外的半导体衬底上的三层。 第二沉积氧化物层形成在半导体衬底的包括去除三层的第一和第二区域的整个表面上。 去除第二区域上的第二沉积氧化物层，并且在包括除去第二沉积氧化物层的第二区域的半导体衬底的整个表面上形成第一热氧化物层。 可以根据本发明制造半导体器件以减少处理时间和降低杂质掺杂分布的变化。 可以控制阻挡氧化物层和高电压栅极氧化物层的厚度。

公开(公告)号：US20050023604A1

公开(公告)日：2005-02-03

申请号：US10844783

申请日：2004-05-13

申请人： Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

发明人： Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

IPC分类号： H01L21/8234 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/76 ,  H01L29/788

CPC分类号： H01L27/11568 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

摘要： The present invention discloses a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same. The method includes providing a semiconductor substrate having a nonvolatile memory region, a first region, and a second region. A triple layer composed of a tunnel oxide layer, a charge storing layer and a first deposited oxide layer on the semiconductor substrate is formed sequentially. The triple layer on the semiconductor substrate except the nonvolatile memory region is then removed. A second deposited oxide layer is formed on an entire surface of the semiconductor substrate including the first and second regions from which the triple layer is removed. The second deposited oxide layer on the second region is removed, and a first thermal oxide layer is formed on the entire surface of the semiconductor substrate including the second region from which the second deposited oxide layer is removed. The semiconductor device can be manufactured according to the present invention to have a reduced processing time and a reduced change of impurity doping profile. The thickness of a blocking oxide layer and a high voltage gate oxide layer can be controlled.

摘要翻译： 本发明公开了一种具有浮动阱式非易失性存储单元的半导体器件及其制造方法。 该方法包括提供具有非易失性存储区域，第一区域和第二区域的半导体衬底。 顺序地形成由半导体衬底上的隧道氧化物层，电荷存储层和第一沉积氧化物层组成的三层。 然后除去非易失性存储区域之外的半导体衬底上的三层。 第二沉积氧化物层形成在半导体衬底的包括去除三层的第一和第二区域的整个表面上。 去除第二区域上的第二沉积氧化物层，并且在包括除去第二沉积氧化物层的第二区域的半导体衬底的整个表面上形成第一热氧化物层。 可以根据本发明制造半导体器件以减少处理时间和降低杂质掺杂分布的变化。 可以控制阻挡氧化物层和高电压栅极氧化物层的厚度。

公开(公告)号：US07045850B2

公开(公告)日：2006-05-16

申请号：US10844783

申请日：2004-05-13

申请人： Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

发明人： Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

IPC分类号： H01L29/76

CPC分类号： H01L27/11568 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

摘要： The present invention discloses a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same. The method includes providing a semiconductor substrate having a nonvolatile memory region, a first region, and a second region. A triple layer composed of a tunnel oxide layer, a charge storing layer and a first deposited oxide layer on the semiconductor substrate is formed sequentially The triple layer on the semiconductor substrate except the nonvolatile memory region is then removed. A second deposited oxide layer is formed on an entire surface of the semiconductor substrate including the first and second regions from which the triple layer is removed. The second deposited oxide layer on the second region is removed, and a first thermal oxide layer is formed on the entire surface of the semiconductor substrate including the second region from which the second deposited oxide layer is removed. The semiconductor device can be manufactured according to the present invention to have a reduced processing time and a reduced change of impurity doping profile. The thickness of a blocking oxide layer and a high voltage gate oxide layer can be controlled.

摘要翻译： 本发明公开了一种具有浮动阱式非易失性存储单元的半导体器件及其制造方法。 该方法包括提供具有非易失性存储区域，第一区域和第二区域的半导体衬底。 依次形成由半导体衬底上的隧道氧化物层，电荷存储层和第一沉积氧化物层构成的三层，然后除去非易失性存储区域之外的半导体衬底上的三层。 第二沉积氧化物层形成在半导体衬底的包括去除三层的第一和第二区域的整个表面上。 去除第二区域上的第二沉积氧化物层，并且在包括除去第二沉积氧化物层的第二区域的半导体衬底的整个表面上形成第一热氧化物层。 可以根据本发明制造半导体器件以减少处理时间和降低杂质掺杂分布的变化。 可以控制阻挡氧化物层和高电压栅极氧化物层的厚度。

公开(公告)号：US07371640B2

公开(公告)日：2008-05-13

申请号：US11378505

申请日：2006-03-17

申请人： Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

发明人： Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

摘要： The present invention discloses a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same. The method includes providing a semiconductor substrate having a nonvolatile memory region, a first region, and a second region. A triple layer composed of a tunnel oxide layer, a charge storing layer and a first deposited oxide layer on the semiconductor substrate is formed sequentially. The triple layer on the semiconductor substrate except the nonvolatile memory region is then removed. A second deposited oxide layer is formed on an entire surface of the semiconductor substrate including the first and second regions from which the triple layer is removed. The second deposited oxide layer on the second region is removed, and a first thermal oxide layer is formed on the entire surface of the semiconductor substrate including the second region from which the second deposited oxide layer is removed. The semiconductor device can be manufactured according to the present invention to have a reduced processing time and a reduced change of impurity doping profile. The thickness of a blocking oxide layer and a high voltage gate oxide layer can be controlled.

摘要翻译： 本发明公开了一种具有浮动阱式非易失性存储单元的半导体器件及其制造方法。 该方法包括提供具有非易失性存储区域，第一区域和第二区域的半导体衬底。 顺序地形成由半导体衬底上的隧道氧化物层，电荷存储层和第一沉积氧化物层组成的三层。 然后除去非易失性存储区域之外的半导体衬底上的三层。 第二沉积氧化物层形成在半导体衬底的包括去除三层的第一和第二区域的整个表面上。 去除第二区域上的第二沉积氧化物层，并且在包括除去第二沉积氧化物层的第二区域的半导体衬底的整个表面上形成第一热氧化物层。 可以根据本发明制造半导体器件以减少处理时间和降低杂质掺杂分布的变化。 可以控制阻挡氧化物层和高电压栅极氧化物层的厚度。

公开(公告)号：US20050048702A1

公开(公告)日：2005-03-03

申请号：US10953553

申请日：2004-09-30

申请人： Geum-Jong Bae ,  Nae-In Lee ,  Sang Kim ,  Ki Kim ,  Jin-Hee Kim ,  In-Wook Cho ,  Sung-Ho Kim ,  Kwang-Wook Koh

发明人： Geum-Jong Bae ,  Nae-In Lee ,  Sang Kim ,  Ki Kim ,  Jin-Hee Kim ,  In-Wook Cho ,  Sung-Ho Kim ,  Kwang-Wook Koh

IPC分类号： H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L21/335

CPC分类号： H01L29/792 ,  H01L29/7923 ,  Y10S438/954

摘要： A local SONOS structure having a two-piece gate and a self-aligned ONO structure includes: a substrate; an ONO structure on the substrate; a first gate layer on and aligned with the ONO structure; a gate insulator on the substrate aside the ONO structure; and a second gate layer on the first gate layer and on the gate insulator. The first and second gate layers are electrically connected together. Together, the ONO structure and first and second gate layers define at least a 1-bit local SONOS structure. A corresponding method of manufacture includes: providing a substrate; forming an ONO structure on the substrate; forming a first gate layer on and aligned with the ONO structure; forming a gate insulator on the substrate aside the ONO structure; forming a second gate layer on the first gate layer and on the gate insulator; and electrically connecting the first and second gate layers.

摘要翻译： 具有两件式门和自对准ONO结构的本地SONOS结构包括：衬底; 基底上的ONO结构; 在ONO结构上并与ONO结构对准的第一栅极层; 衬底上的栅极绝缘体旁边的ONO结构; 以及在第一栅极层上和栅极绝缘体上的第二栅极层。 第一和第二栅极层电连接在一起。 ONO结构和第一和第二栅极层一起定义至少1位本地SONOS结构。 相应的制造方法包括：提供衬底; 在基板上形成ONO结构; 在ONO结构上形成第一栅极层并与其结合; 在衬底上形成栅极绝缘体，除了ONO结构; 在第一栅极层和栅极绝缘体上形成第二栅极层; 并且电连接第一和第二栅极层。

公开(公告)号：US07170794B2

公开(公告)日：2007-01-30

申请号：US10971201

申请日：2004-10-21

申请人： Ki-Chul Kim ,  Byou-Ree Lim ,  Sang-Su Kim ,  Geum-Jong Bae ,  Kwang-Wook Koh

发明人： Ki-Chul Kim ,  Byou-Ree Lim ,  Sang-Su Kim ,  Geum-Jong Bae ,  Kwang-Wook Koh

IPC分类号： G11C11/34

CPC分类号： G11C16/0425

摘要： A programming method of a non-volatile memory device includes a pre-program of the non-volatile memory device, and a main-program of the pre-programmed non-volatile memory device. The non-volatile memory device may include a tunnel dielectric layer, a charge storage layer, a blocking dielectric layer, and a gate electrode, which are sequentially stacked on a semiconductor substrate. The charge storage layer may be an electrically-floated conductive layer, or a dielectric layer having a trap site. By performing a main-program after performing a pre-program, to increase the threshold voltage of the non-volatile memory device, the program current can be effectively reduced.

摘要翻译： 非易失性存储器件的编程方法包括非易失性存储器件的预编程以及预编程的非易失性存储器件的主程序。 非易失性存储器件可以包括依次堆叠在半导体衬底上的隧道介电层，电荷存储层，阻挡介电层和栅电极。 电荷存储层可以是具有陷阱位置的电浮动导电层或介电层。 通过在执行预编程之后执行主程序，为了增加非易失性存储器件的阈值电压，可以有效地减少编程电流。